Design, analysis and application of divisible load scheduling strategies in linear daisy chain networks with system constraints

Ph.DDOCTOR OF PHILOSOPH

Efficient hardware for low latency applications

The design and development of application specific hardware structures has a high degree of complexity. Logic resources are nowadays often not the limit anymore, but the development time. The first part presents a generator which allows defining control and status structures for hardware designs using an abstract high level language. A novel method to inform host systems very efficiently about changes in the register files is presented in the second part. It makes use of a microcode programmable hardware unit. In the third part a fully pipelined address translation mechanism for remote memory access in HPC interconnection networks is presented, which features a new concept to resolve dependency problems. The last part of this thesis addresses the problem of sending TCP messages for a low latency trading application using a hybrid TCP stack implementation that consists of hardware and software components. Furthermore, a simulation environment for the TCP stack is presented