PCI-AER interface for Neuro-inspired Spiking Systems

Address event representation (AER) is a neuromorphic interchip communication protocol that allows for real-time connectivity between huge number neurons located on different chips. By exploiting high speed digital communication circuits (nano-seconds), synaptic neural connections can be time multiplexed (mili-seconds). When building multi-chip muti-layered AER systems it is absolutely necessary to have a computer interface that allows: (a) to read AER interchip traffic; and (b) inject a sequence of events to the AER structure. This paper presents a PCI to AER interface, that dispatches a sequence of events with timing information. It is able to recovery the possible delays introduced by AER bus. It has been implemented in real time hardware using VHDL and tested in a PCI-AER board, developed by authors, that currently capable to send and receive events at a peak rate of 16 Mev/sec, and a typical rate of 10 Mev/secEuropean Commission IST-2001-34124Ministerio de Ciencia y Tecnología TIC-2003-08164-C03-0

Spike-based control monitoring and analysis with Address Event Representation

Neuromorphic engineering tries to mimic biological information processing. Address-Event Representation (AER) is a neuromorphic communication protocol for spiking neurons between different chips. We present a new way to drive robotic platforms using spiking neurons. We have simulated spiking control models for DC motors, and developed a mobile robot (Eddie) controlled only by spikes. We apply AER to the robot control, monitoring and measuring the spike activity inside the robot. The mobile robot is controlled by the AER-Robot tool, and the AER information is sent to a PC using the USBAERmini2 interface.Junta de Andalucía P06-TIC-01417Ministerio de Educación y Ciencia TEC2006-11730-C03-0

Synthetic retina for AER systems development

Neuromorphic engineering tries to mimic biology in information processing. Address-Event Representation (AER) is a neuromorphic communication protocol for spiking neurons between different layers. AER bio-inspired image sensor are called “retina”. This kind of sensors measure visual information not based on frames from real life and generates corresponding events. In this paper we provide an alternative, based on cheap FPGA, to this image sensors that takes images provided by an analog video source (video composite signal), digitalizes it and generates AER streams for testing purposes.Junta de Andalucía P06-TIC-01417Ministerio de Educación y Ciencia TEC2006-11730-C03-0

Embedding Multi-Task Address-Event- Representation Computation

Address-Event-Representation, AER, is a communication protocol that is intended to transfer neuronal spikes between bioinspired chips. There are several AER tools to help to develop and test AER based systems, which may consist of a hierarchical structure with several chips that transmit spikes among them in real-time, while performing some processing. Although these tools reach very high bandwidth at the AER communication level, they require the use of a personal computer to allow the higher level processing of the event information. We propose the use of an embedded platform based on a multi-task operating system to allow both, the AER communication and processing without the requirement of either a laptop or a computer. In this paper, we present and study the performance of an embedded multi-task AER tool, connecting and programming it for processing Address-Event information from a spiking generator.Ministerio de Ciencia e Innovación TEC2006-11730-C03-0

A short curriculum of the robotics and technology of computer lab

Our research Lab is directed by Prof. Anton Civit. It is an interdisciplinary group of 23 researchers that carry out their teaching and researching labor at the Escuela Politécnica Superior (Higher Polytechnic School) and the Escuela de Ingeniería Informática (Computer Engineering School). The main research fields are: a) Industrial and mobile Robotics, b) Neuro-inspired processing using electronic spikes, c) Embedded and real-time systems, d) Parallel and massive processing computer architecture, d) Information Technologies for rehabilitation, handicapped and elder people, e) Web accessibility and usability In this paper, the Lab history is presented and its main publications and research projects over the last few years are summarized.Nuestro grupo de investigación está liderado por el profesor Civit. Somos un grupo multidisciplinar de 23 investigadores que realizan su labor docente e investigadora en la Escuela Politécnica Superior y en Escuela de Ingeniería Informática. Las principales líneas de investigaciones son: a) Robótica industrial y móvil. b) Procesamiento neuro-inspirado basado en pulsos electrónicos. c) Sistemas empotrados y de tiempo real. d) Arquitecturas paralelas y de procesamiento masivo. e) Tecnología de la información aplicada a la discapacidad, rehabilitación y a las personas mayores. f) Usabilidad y accesibilidad Web. En este artículo se reseña la historia del grupo y se resumen las principales publicaciones y proyectos que ha conseguido en los últimos años

Spike Processing on an Embedded Multi-task Computer: Image Reconstruction

There is an emerging philosophy, called Neuro-informatics, contained in the Artificial Intelligence field, that aims to emulate how living beings do tasks such as taking a decision based on the interpretation of an image by emulating spiking neurons into VLSI designs and, therefore, trying to re-create the human brain at its highest level. Address-Event-Representation (AER) is a communication protocol that has embedded part of the processing. It is intended to transfer spikes between bioinspired chips. An AER based system may consist of a hierarchical structure with several chips that transmit spikes among them in real-time, while performing some processing. There are several AER tools to help to develop and test AER based systems. These tools require the use of a computer to allow the higher level processing of the event information, reaching very high bandwidth at the AER communication level. We propose the use of an embedded platform based on a multi-task operating system to allow both, the AER communication and processing without the requirement of either a laptop or a computer. In this paper, we present and study the performance of a new philosophy of a frame-grabber AER tool based on a multi-task environment. This embedded platform is based on the Intel XScale processor which is governed by an embedded GNU/Linux system. We have connected and programmed it for processing Address-Event information from a spiking generator.Ministerio de Educación y Ciencia TEC2006-11730-C03-0

Neuro-Inspired Real-Time USB & PCI to AER Interfaces for Vision Processing

Address-Event-Representation (AER) is an emergent neuromorphic interchip communication protocol that allows for real-time virtual massive connectivity between huge number neurons located on different chips. By exploiting high speed digital communication circuits (with nanoseconds timings), synaptic neural connections can be time multiplexed, while neural activity signals (with mili-seconds timings) are sampled at low frequencies. When building multi-chip muti-layered AER systems it is absolutely necessary to have a computer interface that allows (a) to read AER interchip traffic into the computer and visualize it on screen, and (b) convert conventional frame-based video stream in the computer into AER and inject it at some point of the AER structure. This is necessary for test and debugging of complex AER systems. This paper describes a set of PC interfaces to neuroinspired systems, analyses the performance and power consumption. The interfaces use PCI or USB bus connections that have been developed under an EU project, where they have been tested in a stressed situation.Ministerio de Ciencia y Educación TEC2006-11730-C03-02 (SAMANTA 2)Ministerio de Ciencia y Educación TIN2006- 15617-C03-03Junta de Andalucía P06-TIC-01417Commission of the European Communities IST-2001- 3412

A 5 Meps $100 USB2.0 Address-Event Monitor-Sequencer Interface

This paper describes a high-speed USB2.0 Address- Event Representation (AER) interface that allows simultaneous monitoring and sequencing of precisely timed AER data. This low-cost (<$100), two chip, bus powered interface can achieve sustained AER event rates of 5 megaevents per second (Meps). Several boards can be electrically synchronized, allowing simultaneous synchronized capture from multiple devices. It has three AER ports, one for sequencing, one for monitoring and one for passing through the monitored events. This paper also describes the host software infrastructure that makes the board usable for a heterogeneous mixture of AER devices and that allows recording and playback of recorded data

A geographically distributed bio-hybrid neural network with memristive plasticity

Throughout evolution the brain has mastered the art of processing real-world inputs through networks of interlinked spiking neurons. Synapses have emerged as key elements that, owing to their plasticity, are merging neuron-to-neuron signalling with memory storage and computation. Electronics has made important steps in emulating neurons through neuromorphic circuits and synapses with nanoscale memristors, yet novel applications that interlink them in heterogeneous bio-inspired and bio-hybrid architectures are just beginning to materialise. The use of memristive technologies in brain-inspired architectures for computing or for sensing spiking activity of biological neurons8 are only recent examples, however interlinking brain and electronic neurons through plasticity-driven synaptic elements has remained so far in the realm of the imagination. Here, we demonstrate a bio-hybrid neural network (bNN) where memristors work as "synaptors" between rat neural circuits and VLSI neurons. The two fundamental synaptors, from artificial-to-biological (ABsyn) and from biological-to- artificial (BAsyn), are interconnected over the Internet. The bNN extends across Europe, collapsing spatial boundaries existing in natural brain networks and laying the foundations of a new geographically distributed and evolving architecture: the Internet of Neuro-electronics (IoN).Comment: 16 pages, 10 figure

Memory and information processing in neuromorphic systems

A striking difference between brain-inspired neuromorphic processors and current von Neumann processors architectures is the way in which memory and processing is organized. As Information and Communication Technologies continue to address the need for increased computational power through the increase of cores within a digital processor, neuromorphic engineers and scientists can complement this need by building processor architectures where memory is distributed with the processing. In this paper we present a survey of brain-inspired processor architectures that support models of cortical networks and deep neural networks. These architectures range from serial clocked implementations of multi-neuron systems to massively parallel asynchronous ones and from purely digital systems to mixed analog/digital systems which implement more biological-like models of neurons and synapses together with a suite of adaptation and learning mechanisms analogous to the ones found in biological nervous systems. We describe the advantages of the different approaches being pursued and present the challenges that need to be addressed for building artificial neural processing systems that can display the richness of behaviors seen in biological systems.Comment: Submitted to Proceedings of IEEE, review of recently proposed neuromorphic computing platforms and system