Quadrature Control-Bounded ADCs

In this paper, the design flexibility of the control-bounded analog-to-digital converter principle is demonstrated by considering band-pass analog-to-digital conversion. We show how a low-pass control-bounded analog-to-digital converter can be translated into a band-pass version where the guaranteed stability, converter bandwidth, and signal-to-noise ratio are preserved while the center frequency for conversion can be positioned freely. The proposed converter is validated with behavioral simulations for a variety of filter orders, notch-filter frequencies, and oversampling ratios. Finally, robustness against component variations is demonstrated by Monte Carlo simulations.Comment: 5 pages, 6 figures, submitted to ISCAS 202

A Control-Bounded Quadrature Leapfrog ADC

In this paper, the design flexibility of the control-bounded analog-to-digital converter principle is demonstrated. A band-pass analog-to-digital converter is considered as an application and case study. We show how a low-pass control-bounded analog-to-digital converter can be translated into a band-pass version where the guaranteed stability, converter bandwidth, and signal-to-noise ratio are preserved while the center frequency for conversion can be positioned freely. The proposed converter is validated with behavioral simulations on several filter orders, center frequencies, and oversampling ratios. Additionally, we consider an op-amp circuit realization where the effects of first-order op-amp non-idealities are shown. Finally, robustness against component variations is demonstrated by Monte Carlo simulations.Comment: 13 pages and 16 figure

Design and Simulation of SIGMA DELTA ADC

Analog-to-digital converters play an essential role in modern RF receiver design.Conventional Nyquist converters require analog components that are precise andHighly immune to noise and interference. In contrast, oversampling converters can be implemented using simple and high-tolerance analog components. Moreover,Sampling at high frequency eliminates the need for abrupt cutoffs in the analog antialiasing filters. A technique of noise shaping is used in Ó-Ä converters in addition to oversampling to achieve a high-resolution conversion. A significant advantage of the method is that analog signals are converted using simple and high-tolerance analog circuits, usually a 1-bit comparator, and analog signal processing circuits having a precision that is usually much less than the resolution of the overall converter. In this paper, the design technique for a low-cost first order narrow band sigma-delta modulator in a standard 0.9ìm CMOS technology is described .This circuitry performs the function of an analog-to-digital converter. A first-order 1-bit sigma-delta (Ó-Ä) analog-to-digital converter is designed and simulated using Cadence 0.9ìm CMOS process technology with power supply of 1.8 V through Cadence. The analysis of sigma-delta modulator structures and the design flow were given. The modulator is proved to be robustness, the high performance in stability .The simulation are compared with those from a traditional analog-to-digital converter to prove that sigma-delta is performing better in the case of weak signals acquisition. The design flow consist of a op-amp one of the key component of sigma delta adc which is used for designing of integrator and summing circuit , followed by a high speed comparator and a digital -to-analog convertor in the feedback path

Design of a 14-bit fully differential discrete time delta-sigma modulator

Analog to digital converters play an essential role in modern mixed signal circuit design. Conventional Nyquist-rate converters require analog components that are precise and highly immune to noise and interference. In contrast, oversampling converters can be implemented using simple and high-tolerance analog components. Moreover, sampling at high frequency eliminates the need for abrupt cutoffs in the analog anti-aliasing filters. A noise shaping technique is also used in DS converters in addition to oversampling to achieve a high resolution conversion. A significant advantage of the method is that analog signals are converted using simple and high-tolerance analog circuits, usually a 1-bit comparator, and analog signal processing circuits having a precision that is usually much less than the resolution of the overall converter. In this thesis, a technique to design the discrete time DS converters for 25 kHz baseband signal bandwidth will be described. The noise shaping is achieved using a switched capacitor low-pass integrator around the 1-bit quantizer loop. A latched-type comparator is used as the quantizer of the DS converter. A second order DS modulator is implemented in a TSMC 0.35 µm CMOS technology using a 3.3 V power supply. The peak signal-to-noise ratio (SNR) simulated is 87 dB; the SNDR simulated is 82 dB which corresponds to a resolution of 14 bits. The total static power dissipation is 6.6 mW

A 13-bit, 2.2-MS/s, 55-mW multibit cascade ΣΔ modulator in CMOS 0.7-μm single-poly technology

This paper presents a CMOS 0.7-μm ΣΔ modulator IC that achieves 13-bit dynamic range at 2.2 MS/s with an oversampling ratio of 16. It uses fully differential switched-capacitor circuits with a clock frequency of 35.2 MHz, and has a power consumption of 55 mW. Such a low oversampling ratio has been achieved through the combined usage of fourth-order filtering and multibit quantization. To guarantee stable operation for any input signal and/or initial condition, the fourth-order shaping function has been realized using a cascade architecture with three stages; the first stage is a second-order modulator, while the others are first-order modulators - referred to as a 2-1-1mb architecture. The quantizer of the last stage is 3 bits, while the other quantizers are single bit. The modulator architecture and coefficients have been optimized for reduced sensitivity to the errors in the 3-bit quantization process. Specifically, the 3-bit digital-to-analog converter tolerates 2.8% FS nonlinearity without significant degradation of the modulator performance. This makes the use of digital calibration unnecessary, which is a key point for reduced power consumption. We show that, for a given oversampling ratio and in the presence of 0.5% mismatch, the proposed modulator obtains a larger signal-to-noise-plus-distortion ratio than previous multibit cascade architectures. On the other hand, as compared to a 2-1-1single-bit modulator previously designed for a mixed-signal asymmetrical digital subscriber line modem in the same technology, the modulator in this paper obtains one more bit resolution, enhances the operating frequency by a factor of two, and reduces the power consumption by a factor of four.Comisión Interministerial de Ciencia y Tecnología TIC97-0580European Commission ESPRIT 879

Components for oversampled signal processors

Oversampled converters trade transmission bandwidth for resolution. An idealized model gives an insight into the way in which signals are encoded and thus how they can be manipulated. Oversampling offers a form of signal processing that requires simple processing elements capable of exploiting the growing clock speeds available in integrated solutions. Simultaneously avoids the need for analog circuitry. This paper reviews common operations that can be performed on oversampled signals

Performance Analysis for Time-of-Arrival Estimation with Oversampled Low-Complexity 1-bit A/D Conversion

Analog-to-digtial (A/D) conversion plays a crucial role when it comes to the design of energy-efficient and fast signal processing systems. As its complexity grows exponentially with the number of output bits, significant savings are possible when resorting to a minimum resolution of a single bit. However, then the nonlinear effect which is introduced by the A/D converter results in a pronounced performance loss, in particular for the case when the receiver is operated outside the low signal-to-noise ratio (SNR) regime. By trading the A/D resolution for a moderately faster sampling rate, we show that for time-of-arrival (TOA) estimation under any SNR level it is possible to obtain a low-complexity $1$-bit receive system which features a smaller performance degradation then the classical low SNR hard-limiting loss of $2/\pi$ ($-1.96$ dB). Key to this result is the employment of a lower bound for the Fisher information matrix which enables us to approximate the estimation performance for coarsely quantized receivers with correlated noise models in a pessimistic way

Performance Analysis for Time-of-Arrival Estimation with Oversampled Low-Complexity 1-bit A/D Conversion

Analog-to-digtial (A/D) conversion plays a crucial role when it comes to the design of energy-efficient and fast signal processing systems. As its complexity grows exponentially with the number of output bits, significant savings are possible when resorting to a minimum resolution of a single bit. However, then the nonlinear effect which is introduced by the A/D converter results in a pronounced performance loss, in particular for the case when the receiver is operated outside the low signal-to-noise ratio (SNR) regime. By trading the A/D resolution for a moderately faster sampling rate, we show that for time-of-arrival (TOA) estimation under any SNR level it is possible to obtain a low-complexity $1$-bit receive system which features a smaller performance degradation then the classical low SNR hard-limiting loss of $2/\pi$ ($-1.96$ dB). Key to this result is the employment of a lower bound for the Fisher information matrix which enables us to approximate the estimation performance for coarsely quantized receivers with correlated noise models in a pessimistic way

Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin

A Tool for automated design of sigma-delta modulators using statistical optimization

A tool is presented which starting from high level specifications of SC σδ modulators (resolution, bandwidth and oversampling ratio) calculates first optimum specifications for the building blocks (op-amps, comparator, etc.), and then, optimum sizes for their schematics. At both design levels (high-level synthesis and cell dimensioning), optimization is performed via using statistical techniques and innovative heuristics, which allow global design (independent on the initial conditions) and increased computer efficiency as compared to conventional statistical optimization techniques. The tool has been conceived to be flexible at the high-level part(via the use of an architecture independent, behaviourable modeling approach) and completely open at the cell-design part. Performance of the tool is demonstrated via the automatic design of a 16bit-dynamic range, 8Khz second-order SC σδ modulator in 1.2 μm CMOS technology, for which measurements on a fabricated prototype are reported