Reduced-Order Equivalent-Circuit Models Of Thermal Systems Including Thermal Radiation

We established a general, automatic, and versatile procedure to derive an equivalent circuit for a thermal system using temperature data obtained from FE simulations. The EC topology was deduced from the FE mesh using a robust and general graph-partitioning algorithm. The method was shown to yield models that are independent of the boundary conditions for complicated 3D thermal systems such as an electronic chip. The results are strongly correlated with the geometry, and the EC can be extended to yield variable medium-order models. Moreover, a variety of heat sources and boundary conditions can be accommodated, and the EC models are inherently modular. A reliable method to compute thermal resistors connecting different regions was developed. It appropriately averages several estimates of a thermal resistance where each estimate is obtained using data obtained under different boundary or heating conditions. The concept of fictitious heat sources was used to increase the number of simulation datasets. The method was shown to yield models that are independent of the BCs for complicated 2-D thermal systems such as a 2D cavity. A reliable method to compute thermal resistors connecting different regions was developed. In general, the number of regions required for getting an accurate reduced-order model depends on the complexity of the system to be modeled. We have extended the reduced-order modeling procedure to include a view-factor based thermal radiation heat transfer model by including voltage controlled current sources in the equivalent circuit

myCACTI: A new cache design tool for pipelined nanometer caches

TThe presence of caches in microprocessors has always been one of the most important techniques in bridging the memory wall, or the speed gap between the microprocessor and main memory. This importance is continuously increasing especially as we enter the regime of nanometer process technologies (i.e. 90nm and below), as industry has favored investing a larger and larger fraction of a chip.s transistor budget to improving the on-chip cache. This is the case in practice, as it has proven to be an efficient way to utilize the increasing number of transistors available with each succeeding technology. Consequently, it becomes even more important to have cache design tools that give accurate representations of designs that exist in actual microprocessors. The prevalent cache design tools that are the most widely used in academe are CACTI [Wilton1996] and eCACTI [Mamidipaka2004], and these have proven to be very useful tools not just for cache designers, but also for computer architects. This dissertation will show that both CACTI and eCACTI still contain major limitations and even flaws in their design, making them unsuitable for use in very-deep submicron and nanometer caches, especially pipelined designs. These limitations and flaws will be discussed in detail. This dissertation then introduces a new tool, called myCACTI, that addresses all these limitations and, in addition, introduces major enhancements to the simulation framework. This dissertation then demonstrates the use of myCACTI in the cache design process. Detailed design space explorations are done on multiple cache configurations to produce pareto optimal curves of the caches to show optimal implementations. Detailed studies are also performed to characterize the delay and power dissipation of different cache configurations and implementations. Finally, future directions to the development of myCACTI are identified to show possible ways that the tool can be improved in such a way as to allow even more different kinds of studies to be performed

Optimizing the Thermal Behavior of Subarrayed Data Caches

Designing temperature-aware microarchitectures for microprocessors at new technologies is becoming a critical requirement due to the exponentially increasing on-chip power density. Extremely high power density, thus the very high onchip temperature, not only significantly increases the packaging and cooling costs, but also creates tremendous difficulties in chip leakage control and reliability