ARSITEKTUR PROGRAM PARALEL BERBASIS MESSAGE-PASSING INTERFACE

Komputer bekerja dengan cara mengeksekusi baris-baris kode (program) yang ada di memori utama. Jumlah baris dan kompleksitas kode (program) sangat mempengaruhi banyak sedikitnya sumber daya sistem komputer yang diperlukan untuk mengeksekusi kode (program) yang bersangkutan. Terdapat banyak kasus pada mana kode (program) membutuhkan sumber daya yang sangat besar sehingga diperlukan waktu yang sangat lama untuk menyelesaikan eksekusi. Penelitian ini merupakan sebuah tahap awal untuk menyelidiki apakah arsitektur paralel bisa menjawab tantangan tersebut. Pada tahap awal ini, dibangun sebuah kode (program) dengan arsitektur paralel, dengan menggunakan Message-Passing Interface. Metodologi yang digunakan adalah metodologi pembangunan perangkat lunak dengan model proses prototyping, dilanjutkan dengan analisis hasil eksekusi dan penarikan kesimpulan. Pertama-tama, prototipe dibuat untuk dijalankan di sebuah komputer pribadi. Kemudian prototipe dikembangkan untuk bisa dijalankan pada lima komputer pribadi secara bersamaan. Eksperimen dilakukan menggunakan perangkat keras berupa lima unit komputer bersistem operasi Linux Fedora 19 yang tergabung dalam sebuah sistem jaringan. Penelitian dilakukan dengan bantuan biaya dari Direktorat Jenderal Pendidikan Tinggi melalui skema Hibah Dosen Pemula pendanaan tahun 2013. Kata Kunci: program paralel, Message-Passing Interfac

Optimizing NEURON Simulation Environment Using Remote Memory Access with Recursive Doubling on Distributed Memory Systems

Increase in complexity of neuronal network models escalated the efforts to make NEURON simulation environment efficient. The computational neuroscientists divided the equations into subnets amongst multiple processors for achieving better hardware performance. On parallel machines for neuronal networks, interprocessor spikes exchange consumes large section of overall simulation time. In NEURON for communication between processors Message Passing Interface (MPI) is used. MPI_Allgather collective is exercised for spikes exchange after each interval across distributed memory systems. The increase in number of processors though results in achieving concurrency and better performance but it inversely affects MPI_Allgather which increases communication time between processors. This necessitates improving communication methodology to decrease the spikes exchange time over distributed memory systems. This work has improved MPI_Allgather method using Remote Memory Access (RMA) by moving two-sided communication to one-sided communication, and use of recursive doubling mechanism facilitates achieving efficient communication between the processors in precise steps. This approach enhanced communication concurrency and has improved overall runtime making NEURON more efficient for simulation of large neuronal network models

An Evaluation of One-Sided and Two-Sided Communication Paradigms on Relaxed-Ordering Interconnect

The Cray Gemini interconnect hardware provides multiple transfer mechanisms and out-of-order message delivery to improve communication throughput. In this paper we quantify the performance of one-sided and two-sided communication paradigms with respect to: 1) the optimal available hardware transfer mechanism, 2) message ordering constraints, 3) per node and per core message concurrency. In addition to using Cray native communication APIs, we use UPC and MPI micro-benchmarks to capture one- and two-sided semantics respectively. Our results indicate that relaxing the message delivery order can improve performance up to 4.6x when compared with strict ordering. When hardware allows it, high-level one-sided programming models can already take advantage of message reordering. Enforcing the ordering semantics of two-sided communication comes with a performance penalty. Furthermore, we argue that exposing out-of-order delivery at the application level is required for the next-generation programming models. Any ordering constraints in the language specifications reduce communication performance for small messages and increase the number of active cores required for peak throughput. © 2014 IEEE