14,092 research outputs found
High-Q-factor Al [subscript 2]O[subscript 3] micro-trench cavities integrated with silicon nitride waveguides on silicon
We report on the design and performance of high-Q integrated optical micro-trench cavities on silicon. The microcavities are co-integrated with silicon nitride bus waveguides and fabricated using wafer-scale silicon-photonics-compatible processing steps. The amorphous aluminum oxide resonator material is deposited via sputtering in a single straightforward post-processing step. We examine the theoretical and experimental optical properties of the aluminum oxide micro-trench cavities for different bend radii, film thicknesses and near-infrared wavelengths and demonstrate experimental Q factors of > 10[superscript 6]. We propose that this high-Q micro-trench cavity design can be applied to incorporate a wide variety of novel microcavity materials, including rare-earth-doped films for microlasers, into wafer-scale silicon photonics platforms
PVT-Robust CMOS Programmable Chaotic Oscillator: Synchronization of Two 7-Scroll Attractors
Designing chaotic oscillators using complementary metal-oxide-semiconductor (CMOS) integrated circuit technology for generating multi-scroll attractors has been a challenge. That way, we introduce a current-mode piecewise-linear (PWL) function based on CMOS cells that allow programmable generation of 2–7-scroll chaotic attractors. The mathematical model of the chaotic oscillator designed herein has four coefficients and a PWL function, which can be varied to provide a high value of the maximum Lyapunov exponent. The coefficients are implemented electronically by designing operational transconductance amplifiers that allow programmability of their transconductances. Design simulations of the chaotic oscillator are provided for the 0.35μ m CMOS technology. Post-layout and process–voltage–temperature (PVT) variation simulations demonstrate robustness of the multi-scroll chaotic attractors. Finally, we highlight the synchronization of two seven-scroll attractors in a master–slave topology by generalized Hamiltonian forms and observer approach. Simulation results show that the synchronized CMOS chaotic oscillators are robust to PVT variations and are suitable for chaotic secure communication applications.Universidad Autónoma de Tlaxcala CACyPI-UATx-2017Program to Strengthen Quality in Educational Institutions C/PFCE-2016-29MSU0013Y-07-23National Council for Science and Technology 237991 22284
Energy challenges for ICT
The energy consumption from the expanding use of information and communications technology (ICT) is unsustainable with present drivers, and it will impact heavily on the future climate change. However, ICT devices have the potential to contribute signi - cantly to the reduction of CO2 emission and enhance resource e ciency in other sectors, e.g., transportation (through intelligent transportation and advanced driver assistance systems and self-driving vehicles), heating (through smart building control), and manu- facturing (through digital automation based on smart autonomous sensors). To address the energy sustainability of ICT and capture the full potential of ICT in resource e - ciency, a multidisciplinary ICT-energy community needs to be brought together cover- ing devices, microarchitectures, ultra large-scale integration (ULSI), high-performance computing (HPC), energy harvesting, energy storage, system design, embedded sys- tems, e cient electronics, static analysis, and computation. In this chapter, we introduce challenges and opportunities in this emerging eld and a common framework to strive towards energy-sustainable ICT
Improving practical sensitivity of energy optimized wake-up receivers: proof of concept in 65nm CMOS
We present a high performance low-power digital base-band architecture,
specially designed for an energy optimized duty-cycled wake-up receiver scheme.
Based on a careful wake-up beacon design, a structured wake-up beacon detection
technique leads to an architecture that compensates for the implementation loss
of a low-power wake-up receiver front-end at low energy and area costs. Design
parameters are selected by energy optimization and the architecture is easily
scalable to support various network sizes. Fabricated in 65nm CMOS, the digital
base-band consumes 0.9uW (V_DD=0.37V) in sub-threshold operation at 250kbps,
with appropriate 97% wake-up beacon detection and 0.04% false alarm
probabilities. The circuit is fully functional at a minimum V_DD of 0.23V at
f_max=5kHz and 0.018uW power consumption. Based on these results we show that
our digital base-band can be used as a companion to compensate for front-end
implementation losses resulting from the limited wake-up receiver power budget
at a negligible cost. This implies an improvement of the practical sensitivity
of the wake-up receiver, compared to what is traditionally reported.Comment: Submitted to IEEE Sensors Journa
Design of A Low Power Low Voltage CMOS Opamp
In this paper a CMOS operational amplifier is presented which operates at 2V
power supply and 1microA input bias current at 0.8 micron technology using non
conventional mode of operation of MOS transistors and whose input is depended
on bias current. The unique behaviour of the MOS transistors in subthreshold
region not only allows a designer to work at low input bias current but also at
low voltage. While operating the device at weak inversion results low power
dissipation but dynamic range is degraded. Optimum balance between power
dissipation and dynamic range results when the MOS transistors are operated at
moderate inversion. Power is again minimised by the application of input
dependant bias current using feedback loops in the input transistors of the
differential pair with two current substractors. In comparison with the
reported low power low voltage opamps at 0.8 micron technology, this opamp has
very low standby power consumption with a high driving capability and operates
at low voltage. The opamp is fairly small (0.0084 mm 2) and slew rate is more
than other low power low voltage opamps reported at 0.8 um technology [1,2].
Vittoz at al [3] reported that slew rate can be improved by adaptive biasing
technique and power dissipation can be reduced by operating the device in weak
inversion. Though lower power dissipation is achieved the area required by the
circuit is very large and speed is too small. So, operating the device in
moderate inversion is a good solution. Also operating the device in
subthreshold region not only allows lower power dissipation but also a lower
voltage operation is achieved.Comment: 8 Pages, VLSICS Journa
A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects
Interconnect architectures which leverage high-bandwidth optical channels offer a promising solution to address the increasing chip-to-chip I/O bandwidth demands. This paper describes a dense, high-speed, and low-power CMOS optical interconnect transceiver architecture. Vertical-cavity surface-emitting laser (VCSEL) data rate is extended for a given average current and corresponding reliability level with a four-tap current summing FIR transmitter. A low-voltage integrating and double-sampling optical receiver front-end provides adequate sensitivity in a power efficient manner by avoiding linear high-gain elements common in conventional transimpedance-amplifier (TIA) receivers. Clock recovery is performed with a dual-loop architecture which employs baud-rate phase detection and feedback interpolation to achieve reduced power consumption, while high-precision phase spacing is ensured at both the transmitter and receiver through adjustable delay clock buffers. A prototype chip fabricated in 1 V 90 nm CMOS achieves 16 Gb/s operation while consuming 129 mW and occupying 0.105 mm^2
- …