Implementation of Fast, Low Power and Area Efficient Carry Select Adder

One of the fastest adders is Carry Select Adder (CSLA) and it perform fast arithmetic functions in many data processing processors. A conventional CSLA has less carry propagation delay (CPD) than ripple carry adder (RCA). A compromise between RCA and carry look ahead adder is provided by Carry select adder. For the CSLA new logic is proposed by reducing redundant logic operations present in conventional CSLA. In the proposed scheme, schedule the carry select (CS) operation before final sum calculation. which is different approach from the conventional. Two carry words ( cin = 0 and 1) bit patterns and fixed cin bits use for generation units and CS logic optimization. Optimized logic units is used to obtain an efficient CSLA design. The proposed work is carried out using Modelsim SE 6.3f and Quatus2 software. DOI: 10.17762/ijritcc2321-8169.16046

Optimized Design of Parallel Carry-Select Adders

3In this paper a novel gate-level strategy for designing Carry Select adders is proposed. The strategy is more general than the previously proposed techniques, and accounts for the dependence of multiplexer delay on its fan-out. Moreover, the strategy is simple and systematic, and is helpful for designing Carry Select adders with a pencil-and-paper approach. An approximate expression of the minimum delay achievable is derived to estimate performance before carrying out the design. The proposed strategy is validated in more than 1,000 adders. Analysis confirms that the strategy leads to a delay which is minimal in most cases, and always within 5.7%.reservedmixedM. Alioto; M. Poli; G. PalumboAlioto, MASSIMO BRUNO CRIS; Poli, Massimo; G., Palumb