A recursive paradigm to solve Boolean relations

A Boolean relation can specify some types of flexibility of a combinational circuit that cannot be expressed with don't cares. Several problems in logic synthesis, such as Boolean decomposition or multilevel minimization, can be modeled with Boolean relations. However, solving Boolean relations is a computationally expensive task. This paper presents a novel recursive algorithm for solving Boolean relations. The algorithm has several features: efficiency, wide exploration of solutions, and customizable cost function. The experimental results show the applicability of the method in logic minimization problems and tangible improvements with regard to previous heuristic approaches

Logic Synthesis for Established and Emerging Computing

Logic synthesis is an enabling technology to realize integrated computing systems, and it entails solving computationally intractable problems through a plurality of heuristic techniques. A recent push toward further formalization of synthesis problems has shown to be very useful toward both attempting to solve some logic problems exactly--which is computationally possible for instances of limited size today--as well as creating new and more powerful heuristics based on problem decomposition. Moreover, technological advances including nanodevices, optical computing, and quantum and quantum cellular computing require new and specific synthesis flows to assess feasibility and scalability. This review highlights recent progress in logic synthesis and optimization, describing models, data structures, and algorithms, with specific emphasis on both design quality and emerging technologies. Example applications and results of novel techniques to established and emerging technologies are reported

Optimization of combinational logic circuits based on compatible gates

Abstract- Thts paper prmenta a set of new teelmiques for the nptimtzattmr of multiple-level combtnattorud Boolean networks. Such teehntquea are breed on a temporary tmnsfonnatlon of the networ& tnto an internally unste one. We descrtbe tirat a teebnique baaed upon the seleetion of appropriate multiple-output subnetwo~s (consisting of s~c.slled comprztible gates) whose local functions can be opthntzed sttmdtaneoualy. We then generalize the method to larger subsets of tmate gates. Beeauae shntdtaneoua opttmizatton of local functions ean take place, our methods are more powerful and general than Boolean optimization methods using don t cares, where only single-gate opti. ndzatton am be performed. In addttton, our methods rvpmaent a more efficient alternative to Boolean rvlations-b=d opttndzation procedures beeauae the problem can be mndeled by a mate covertng problem tnstead of the more difficult binate eoverhtg problem. The method ts implemented in program achilks and compares favorably to ~S.

Optimization of Combinational Logic Circuits Based on Compatible Gates

This paper presents a set of new techniques for the optimization of multiple-level combinational Boolean networks. We describe first a technique based upon the selection of appropriate multiple-output subnetworks (consisting of so-called compatible gates) whose local functions can be optimized simultaneously. We then generalize the method to larger and more arbitrary subsets of gates. Because simultaneous optimization of local functions can take place, our methods are more powerful and general than Boolean optimization methods using don't cares , where only single-gate optimization can be performed. In addition, our methods represent a more efficient alternative to optimization procedures based on Boolean relations because the problem can be modeled by a unate covering problem instead of the more difficult binate covering problem. The method is implemented in program ACHILLES and compares favorably to SIS