3 research outputs found
Preference-Guided Register Assignment
Abstract. This paper deals with coalescing in SSA-based register allo-cation. Current coalescing techniques all require the interference graph to be built. This is generally considered to be too compile-time intensive for just-in-time compilation. In this paper, we present a biased coloring approach that gives results similar to standalone coalescers while signif-icantly reducing compile time.
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Optimal register sharing for high-level synthesis of SSA form programs
Register sharing for high-level synthesis of programs represented in static single assignment (SSA) form is proven to have a polynomial-time solution. Register sharing is modeled as a graph-coloring problem. Although graph coloring is NIP-Complete in the general case, an interference graph constructed for a program in SSA form probably belongs to the class of chordal graphs that have an optimal O(|V| + |E|) time algorithm. Chordal graph coloring reduces the number of registers allocated to the program by as much as 86% and 64.93% on average compared to linear scan register allocation
๋น ๋ฅธ ์ฑ๋ฅ์กฐ๊ฑด ๋ง์กฑ์ ์ํ ์๊ณ๊ฒฝ๋ก๋ฅผ ๊ณ ๋ คํ๋ ์์ ์์ค ํฉ์ฑ
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ผ๋ฌธ (๋ฐ์ฌ)-- ์์ธ๋ํ๊ต ๋ํ์ : ์ ๊ธฐยท์ปดํจํฐ๊ณตํ๋ถ, 2014. 2. ์ต๊ธฐ์.Rapid advancement of process technology enables designers to integrate various functions onto a single chip and to realize diverse requirements of customers, but productivity of system designers has improved too slowly to make optimal design in time-to-market. Since designing at higher levels of abstraction reduces the number of design instances to be considered to acquire an optimal design, it improves quality of system as well as reduces design time and cost. High-level synthesis, which maps behavioral description models to register-transfer models, can improve design productivity drastically, and thus, it has been one of the important issues in electronic system level design.
Centralized controllers commonly used in high-level synthesis often require long wires and cause high load capacitance, and that is why critical paths typically occur on paths from controllers to data registers instead of paths from data registers to data registers. However, conventional high-level synthesis has focused on delays within a datapath, making it difficult to solve the timing closure problem during physical synthesis.
This thesis presents hardware architecture with a distributed controller, which makes the timing closure problem much easier. A novel critical-path-aware high-level synthesis flow is also presented for synthesizing such hardware through datapath partitioning, register binding, and controller optimization. We explore the design space related to the number of partitions, which is an important design parameter for target architecture. According to our experiments, the proposed approach reduces the critical path delay excluding FUs by 29.3% and that including FUs by 10.0%, with 2.2% area overhead on average compared to centralized controller architecture. We also propose two approaches, clock gating and register constrained flow, to alleviate high peak current problem which is caused by the proposed approach. These approaches suppress the peak current overhead to keep it less than 3.6%.Chapter 1 Introduction 1
Chapter 2 Background 7
2.1 High-level Synthesis 7
2.2 Subtasks of High-level Synthesis 8
2.2.1 Operation Scheduling and FU Binding 8
2.2.2 Register Binding 10
2.2.3 Controller Synthesis 11
2.2.4 Functional Pipelining Technique for High-level Synthesis 11
2.3 Centralized Controller Architecture 12
2.4 Design Closure Problem in High-level Synthesis 15
2.5 Thesis Contribution 18
Chapter 3 Target Architecture and Overall flow 21
3.1 Target Architecture 21
3.2 Overall flow 23
Chapter 4 Critical-Path-Aware Datapath Partitioning 27
4.1 Introduction 27
4.2 Problem Formulation 30
4.3 Proposed Algorithm 32
4.4 Exploring Design Space for the Number of Partitions 36
Chapter 5 Critical-Path-Aware Register Binding 39
5.1 Introduction 39
5.2 Problem Formulation 40
5.3 Proposed Algorithm 43
Chapter 6 Critical-Path-Aware Controller Optimization 49
6.1 Introduction 49
6.2 Problem Formulation 50
6.3 Proposed Algorithm 55
Chapter 7 Evaluation 63
7.1 Experimental Setup 63
7.2 Design Parameters and Computation Time 66
7.3 Analysis Critical Path Delay on Distributed Controller Architecture 68
7.4 Analysis of Performance and Area 70
7.5 Energy Consumption 78
7.6 Analysis on Register Overhead 80
7.6.1 Clock Gating Approach 81
7.6.2 Register Constrained Approach 84
7.6.3 Combined Approach 86
7.7 Join to Conventional Optimization Techniques on HLS 87
7.8 Comparison with DRFM Binding Approach 87
Chapter 8 Conclusion and Future Work 89
8.1 Summary 89
8.2 Future Work 90
Bibliography 93
Abstract in Korean 103Docto