A design tool for high-resolution high-frequency cascade continuous- time Σ∆ modulators

Event: Microtechnologies for the New Millennium, 2007, Maspalomas, Gran Canaria, SpainThis paper introduces a CAD methodology to assist the de signer in the implementation of continuous-time (CT) cas- cade Σ∆ modulators. The salient features of this methodology ar e: (a) flexible behavioral modeling for optimum accuracy- efficiency trade-offs at different stages of the top-down synthesis process; (b) direct synthesis in the continuous-time domain for minimum circuit complexity and sensitivity; a nd (c) mixed knowledge-based and optimization-based architec- tural exploration and specification transmission for enhanced circuit performance. The applicability of this methodology will be illustrated via the design of a 12 bit 20 MHz CT Σ∆ modulator in a 1.2V 130nm CMOS technology.Ministerio de Ciencia y Educación TEC2004-01752/MICMinisterio de Industria, Turismo y Comercio FIT-330100-2006-134 SPIRIT Projec

Accurate Settling-Time Modeling and Design Procedures for Two-Stage Miller-Compensated Amplifiers for Switched-Capacitor Circuits

We present modeling techniques for accurate estimation of settling errors in switched-capacitor (SC) circuits built with Miller-compensated operational transconductance amplifiers (OTAs). One distinctive feature of the proposal is the computation of the impact of signal levels (on both the model parameters and the model structure) as they change during transient evolution. This is achieved by using an event-driven behavioral approach that combines small- and large-signal behavioral descriptions and keeps track of the amplifier state after each clock phase. Also, SC circuits are modeled under closed-loop conditions to guarantee that the results remain close to those obtained by electrical simulation of the actual circuits. Based on these models, which can be regarded as intermediate between the more established small-signal approach and full-fledged simulations, design procedures for dimensioning SC building blocks are presented whose targets are system-level specifications (such as ENOB and SNDR) instead of OTA specifications. The proposed techniques allow to complete top-down model-based designs with 0.3-b accuracy.Ministerio de Educación y Ciencia TEC2006-03022Junta de Andalucía TIC-0281

Paper Session I-A - Is It SEP Yet?

This paper is a presentation of the results of recent studies indicating that solar electric propulsion can be implemented in a Discovery-class scenario to permit an affordable exploration of comets and asteroids in the very near future. Gallium arsenide solar array technology, the availability of space-qualified ion and plasma thrusters, and appropriate power conditioning equipment are cited as enabling factors for an exciting class of missions that can permit exploration of a number of asteroids and short-period comets, using the Delta launch vehicle, before the turn of the century. Launch requirements are about 993 kg to C$ = 10 km^/s^ for an assumed 50 to 75 kg complement of science instruments. An advantageous feature of electric propulsion is that the high installed power level, unnecessary for propulsion during rendezvous, enables high science data rates from most potential targets

High-resolution distributed sampling of bandlimited fields with low-precision sensors

The problem of sampling a discrete-time sequence of spatially bandlimited fields with a bounded dynamic range, in a distributed, communication-constrained, processing environment is addressed. A central unit, having access to the data gathered by a dense network of fixed-precision sensors, operating under stringent inter-node communication constraints, is required to reconstruct the field snapshots to maximum accuracy. Both deterministic and stochastic field models are considered. For stochastic fields, results are established in the almost-sure sense. The feasibility of having a flexible tradeoff between the oversampling rate (sensor density) and the analog-to-digital converter (ADC) precision, while achieving an exponential accuracy in the number of bits per Nyquist-interval per snapshot is demonstrated. This exposes an underlying ``conservation of bits'' principle: the bit-budget per Nyquist-interval per snapshot (the rate) can be distributed along the amplitude axis (sensor-precision) and space (sensor density) in an almost arbitrary discrete-valued manner, while retaining the same (exponential) distortion-rate characteristics. Achievable information scaling laws for field reconstruction over a bounded region are also derived: With N one-bit sensors per Nyquist-interval, $\Theta(\log N)$ Nyquist-intervals, and total network bitrate $R_{net} = \Theta((\log N)^2)$ (per-sensor bitrate $\Theta((\log N)/N)$), the maximum pointwise distortion goes to zero as $D = O((\log N)^2/N)$ or $D = O(R_{net} 2^{-\beta \sqrt{R_{net}}})$. This is shown to be possible with only nearest-neighbor communication, distributed coding, and appropriate interpolation algorithms. For a fixed, nonzero target distortion, the number of fixed-precision sensors and the network rate needed is always finite.Comment: 17 pages, 6 figures; paper withdrawn from IEEE Transactions on Signal Processing and re-submitted to the IEEE Transactions on Information Theor

HDR Imaging With One-Bit Quantization

Modulo sampling and dithered one-bit quantization frameworks have emerged as promising solutions to overcome the limitations of traditional analog-to-digital converters (ADCs) and sensors. Modulo sampling, with its high-resolution approach utilizing modulo ADCs, offers an unlimited dynamic range, while dithered one-bit quantization offers cost-efficiency and reduced power consumption while operating at elevated sampling rates. Our goal is to explore the synergies between these two techniques, leveraging their unique advantages, and to apply them to non-bandlimited signals within spline spaces. One noteworthy application of these signals lies in High Dynamic Range (HDR) imaging. In this paper, we expand upon the Unlimited One-Bit (UNO) sampling framework, initially conceived for bandlimited signals, to encompass non-bandlimited signals found in the context of HDR imaging. We present a novel algorithm rigorously examined for its ability to recover images from one-bit modulo samples. Additionally, we introduce a sufficient condition specifically designed for UNO sampling to perfectly recover non-bandlimited signals within spline spaces. Our numerical results vividly demonstrate the effectiveness of UNO sampling in the realm of HDR imaging.Comment: arXiv admin note: text overlap with arXiv:2308.0069

Regression modeling for digital test of ΣΔ modulators

The cost of Analogue and Mixed-Signal circuit testing is an important bottleneck in the industry, due to timeconsuming verification of specifications that require state-ofthe- art Automatic Test Equipment. In this paper, we apply the concept of Alternate Test to achieve digital testing of converters. By training an ensemble of regression models that maps simple digital defect-oriented signatures onto Signal to Noise and Distortion Ratio (SNDR), an average error of 1:7% is achieved. Beyond the inference of functional metrics, we show that the approach can provide interesting diagnosis information.Ministerio de Educación y Ciencia TEC2007-68072/MICJunta de Andalucía TIC 5386, CT 30

Design methodology for low-jitter differential clock recovery circuits in high performance ADCs

This paper presents a design methodology for the simultaneous optimization of jitter and power consumption in ultra-low jitter clock recovery circuits (<100fsrms) for high-performance ADCs. The key ideas of the design methodology are: a) a smart parameterization of transistor sizes to have smooth dependence of specifications on the design variables, b) based on this parameterization, carrying out a design space sub-sampling which allows capturing the whole circuit performance for reducing computation resources and time during optimization. The proposed methodology, which can easily incorporate process voltage and temperature (PVT) variations, has been used to perform a systematic design space exploration that provides sub-100fs jitter clock recovery circuits in two CMOS commercial processes at different technological nodes (1.8V 0.18μm and 1.2V 90nm). Post-layout simulation results for a case of study with typical jitter of 68fs for a 1.8V 80dB-SNDR 100Msps Pipeline ADC application are also shown as demonstrator.Gobierno de España TEC2015-68448-REuropean Space Agency 4000108445-13-NL-R

Modeling, Optimization and Testing for Analog/Mixed-Signal Circuits in Deeply Scaled CMOS Technologies

As CMOS technologies move to sub-100nm regions, the design and verification for analog/mixed-signal circuits become more and more difficult due to the problems including the decrease of transconductance, severe gate leakage and profound mismatches. The increasing manufacturing-induced process variations and their impacts on circuit performances make the already complex circuit design even more sophisticated in the deeply scaled CMOS technologies. Given these barriers, efforts are needed to ensure the circuits are robust and optimized with consideration of parametric variations. This research presents innovative computer-aided design approaches to address three such problems: (1) large analog/mixed-signal performance modeling under process variations, (2) yield-aware optimization for complex analog/mixedsignal systems and (3) on-chip test scheme development to detect and compensate parametric failures. The first problem focus on the efficient circuit performance evaluation with consideration of process variations which serves as the baseline for robust analog circuit design. We propose statistical performance modeling methods for two popular types of complex analog/mixed-signal circuits including Sigma-Delta ADCs and charge-pump PLLs. A more general performance modeling is achieved by employing a geostatistics motivated performance model (Kriging model), which is accurate and efficient for capturing stand-alone analog circuit block performances. Based on the generated block-level performance models, we can solve the more challenging problem of yield-aware system optimization for large analog/mixed-signal systems. Multi-yield pareto fronts are utilized in the hierarchical optimization framework so that the statistical optimal solutions can be achieved efficiently for the systems. We further look into on-chip design-for-test (DFT) circuits in analog systems and solve the problems of linearity test in ADCs and DFT scheme optimization in charge-pump PLLs. Finally a design example of digital intensive PLL is presented to illustrate the practical applications of the modeling, optimization and testing approaches for large analog/mixed-signal systems