Hardware aware tiling optimization for multi-core systems

This paper presents a proposition of the new tool which improves tiling efficiencyfor given hardware architecture. This article also describes the correlationbetween changing hardware architecture and methods of software optimization.First chapter includes short description of the change in hardware architecturewhich has occurred in recent 10 years. The second chapter provides an overviewof tools which will be used in further research. The consecutive sections containdescription of proposed hardware-aware tool for optimal tiling

Machine Learning in Compiler Optimization

In the last decade, machine learning based compilation has moved from an an obscure research niche to a mainstream activity. In this article, we describe the relationship between machine learning and compiler optimisation and introduce the main concepts of features, models, training and deployment. We then provide a comprehensive survey and provide a road map for the wide variety of different research areas. We conclude with a discussion on open issues in the area and potential research directions. This paper provides both an accessible introduction to the fast moving area of machine learning based compilation and a detailed bibliography of its main achievements