Online Scheduled Execution of Quantum Circuits Protected by Surface Codes

Quantum circuits are the preferred formalism for expressing quantum information processing tasks. Quantum circuit design automation methods mostly use a waterfall approach and consider that high level circuit descriptions are hardware agnostic. This assumption has lead to a static circuit perspective: the number of quantum bits and quantum gates is determined before circuit execution and everything is considered reliable with zero probability of failure. Many different schemes for achieving reliable fault-tolerant quantum computation exist, with different schemes suitable for different architectures. A number of large experimental groups are developing architectures well suited to being protected by surface quantum error correcting codes. Such circuits could include unreliable logical elements, such as state distillation, whose failure can be determined only after their actual execution. Therefore, practical logical circuits, as envisaged by many groups, are likely to have a dynamic structure. This requires an online scheduling of their execution: one knows for sure what needs to be executed only after previous elements have finished executing. This work shows that scheduling shares similarities with place and route methods. The work also introduces the first online schedulers of quantum circuits protected by surface codes. The work also highlights scheduling efficiency by comparing the new methods with state of the art static scheduling of surface code protected fault-tolerant circuits.Comment: accepted in QI

Resource Optimized Quantum Architectures for Surface Code Implementations of Magic-State Distillation

Quantum computers capable of solving classically intractable problems are under construction, and intermediate-scale devices are approaching completion. Current efforts to design large-scale devices require allocating immense resources to error correction, with the majority dedicated to the production of high-fidelity ancillary states known as magic-states. Leading techniques focus on dedicating a large, contiguous region of the processor as a single "magic-state distillation factory" responsible for meeting the magic-state demands of applications. In this work we design and analyze a set of optimized factory architectural layouts that divide a single factory into spatially distributed factories located throughout the processor. We find that distributed factory architectures minimize the space-time volume overhead imposed by distillation. Additionally, we find that the number of distributed components in each optimal configuration is sensitive to application characteristics and underlying physical device error rates. More specifically, we find that the rate at which T-gates are demanded by an application has a significant impact on the optimal distillation architecture. We develop an optimization procedure that discovers the optimal number of factory distillation rounds and number of output magic states per factory, as well as an overall system architecture that interacts with the factories. This yields between a 10x and 20x resource reduction compared to commonly accepted single factory designs. Performance is analyzed across representative application classes such as quantum simulation and quantum chemistry.Comment: 16 pages, 14 figure

Noise-Adaptive Compiler Mappings for Noisy Intermediate-Scale Quantum Computers

A massive gap exists between current quantum computing (QC) prototypes, and the size and scale required for many proposed QC algorithms. Current QC implementations are prone to noise and variability which affect their reliability, and yet with less than 80 quantum bits (qubits) total, they are too resource-constrained to implement error correction. The term Noisy Intermediate-Scale Quantum (NISQ) refers to these current and near-term systems of 1000 qubits or less. Given NISQ's severe resource constraints, low reliability, and high variability in physical characteristics such as coherence time or error rates, it is of pressing importance to map computations onto them in ways that use resources efficiently and maximize the likelihood of successful runs. This paper proposes and evaluates backend compiler approaches to map and optimize high-level QC programs to execute with high reliability on NISQ systems with diverse hardware characteristics. Our techniques all start from an LLVM intermediate representation of the quantum program (such as would be generated from high-level QC languages like Scaffold) and generate QC executables runnable on the IBM Q public QC machine. We then use this framework to implement and evaluate several optimal and heuristic mapping methods. These methods vary in how they account for the availability of dynamic machine calibration data, the relative importance of various noise parameters, the different possible routing strategies, and the relative importance of compile-time scalability versus runtime success. Using real-system measurements, we show that fine grained spatial and temporal variations in hardware parameters can be exploited to obtain an average $2.9$x (and up to $18$x) improvement in program success rate over the industry standard IBM Qiskit compiler.Comment: To appear in ASPLOS'1

Large Scale Modular Quantum Computer Architecture with Atomic Memory and Photonic Interconnects

The practical construction of scalable quantum computer hardware capable of executing non-trivial quantum algorithms will require the juxtaposition of different types of quantum systems. We analyze a modular ion trap quantum computer architecture with a hierarchy of interactions that can scale to very large numbers of qubits. Local entangling quantum gates between qubit memories within a single register are accomplished using natural interactions between the qubits, and entanglement between separate registers is completed via a probabilistic photonic interface between qubits in different registers, even over large distances. We show that this architecture can be made fault-tolerant, and demonstrate its viability for fault-tolerant execution of modest size quantum circuits

Numerical and analytical studies of quantum error correction

A reliable large-scale quantum computer, if built, can solve many real-life problems exponentially faster than the existing digital devices. The biggest obstacle to building one is that they are extremely sensitive and error-prone regardless of the selection of physical implementation. Both data storage and data manipulation require careful implementation and precise control due to its quantum mechanical nature. For the development of a practical and scalable computer, it is essential to identify possible quantum errors and reduce them throughout every layer of the hierarchy of quantum computation. In this dissertation, we present our investigation into new methods to reduce errors in quantum computers from three different directions: quantum memory, quantum control, and quantum error correcting codes. For quantum memory, we pursue the potential of the quantum equivalent of a magnetic hard drive using two-body-interaction structures in fractal dimensions. With regard to quantum control, we show that it is possible to arbitrarily reduce error when manipulating multiple quantum bits using a technique popular in nuclear magnetic resonance. Finally, we introduce an efficient tool to study quantum error correcting codes and present analysis of the codes' performance on model quantum architectures.Ph.D