Implementation of Static and Semi-Static Versions of a 24+8x8 Quad-rail NULL Convention Multiply and Accumulate Unit

This paper focuses on implementing a 2s complement 8x8 dual-rail bit-wise pipelined multiplier using the asynchronous null convention logic (NCL) paradigm. The design utilizes a Wallace tree for partial product summation, and is implemented and simulated in VHDL, the transistor level, and the physical level, using a 1.8V 0.18mum TSMC CMOS process. The multiplier is realized using both static and semi-static versions of the NCL gates; and these two implementations are compared in terms of area, power, and speed

A Framework for the Detection of Crosstalk Noise in FPGAs

In recent years, crosstalk noise has emerged a serious problem because more and more devices and wires have been packed on electronic chips. As integrated circuits are migrated to more advanced technologies, it has become clear that crosstalk noise is the important phenomenon that must be taken into account. Despite of being more immune to crosstalk noise than their ASIC (application specific integrated circuit) counterparts, the dense interconnected structures of FPGAs (field programmable gate arrays) invite more vulnerabilities with crosstalk noise. Due to the lack of electrical detail concerning FPGA devices it is quite difficult to test the faults affected by crosstalk noise. This paper proposes a new approach for detecting the effects such as glitches and delays in transition that are due to crosstalk noise in FPGAs. This approach is similar to the BIST (built-in self test) technique in that it incorporates the test pattern generator to generate the test vectors and the analyzer to analyze the crosstalk faults without any overhead for testing

Entwicklung einer effizienten Entwurfsraumanalyse zur Optimierung der Leistungsaufnahme von Networks-on-Chip

In der Arbeit werden Networks-on-Chip untersucht. Ein Teil beschäftigt sich mit dem Aufbau und den Eigenschaften von Links bzw. allgemein parallelen on-Chip-Leitungen. Speziell wird auf Crosstalk und eine digitale Methode, diesen Effekt zu messen, eingegangen. Im zweiten Teil der Arbeit wird ein NoC-Router untersucht und dessen Implementierung beschrieben. Aus diesen Erkenntnissen wird eine Methode entwickelt, den Entwurfsraum für ein NoC-basiertes System zu analysieren und so die optimale Kommunikationsarchitektur für eine bestimmte Anwendung zu bestimmen