Application of a Stable Latency Insertion Method for Simulations of Power Distribution Networks

This paper presents an application of a stable implementation of the latency insertion method for simulations of power distribution networks (PDN). Traditionally, simulations of PDNs poses a considerable challenge due to their large circuit sizes. While the latency insertion method can be applied to simulate these networks, the existence of low latency elements results in a more stringent stability criterion which reduces the efficiency of the method. Using the improved formulation, a latency insertion method that is free from the stability criteria is obtained, which results in no limitation on the size of the time step

Linear-time 3-D thermal methods for transient electro-thermal simulations

Both users and industries demand devices and systems with higher performances and better reliabilities. To achieve both, an electro-thermal simulator is needed as the thermal aspect of a device, such as the temperature, can play a big role on its reliability. By doing just the electrical simulation, an engineer cannot possibly determine the temperature of operation, and thus cannot know whether the design is reliable. The approach of this work is to separate an electro-thermal simulator into two components, one takes care of the electrical part while the other one takes care of the thermal part. The main focus of this work is the thermal simulator. Two thermal simulators are discussed: the latency insertion method (LIM) and the Douglass-Gunn method (DGM). These two methods are chosen because they have linear complexity, which is valuable when doing a simulation on a large system from the simulation time perspective. In-depth formulations are covered for these two methods. The problem of interest is a large metal-oxide semiconductor field-effect transistor (MOSFET). Simulation results of both LIM and DGM are provided and validated using Ansys Icepak, a commercially available thermal analysis tool. Lastly, some comparisons and future work are provided, to improve results and take further steps from this work

On-Chip Power Supply Noise: Scaling, Suppression and Detection

Design metrics such as area, timing and power are generally considered as the primary criteria in the design of modern day circuits, however, the minimization of power supply noise, among other noise sources, is appreciably more important since not only can it cause a degradation in these parameters but can cause entire chips to fail. Ensuring the integrity of the power supply voltage in the power distribution network of a chip is therefore crucial to both building reliable circuits as well as preventing circuit performance degradation. Power supply noise concerns, predicted over two decades ago, continue to draw significant attention, and with present CMOS technology projected to keep on scaling, it is shown in this work that these issues are not expected to diminish. This research also considers the management and on-chip detection of power supply noise. There are various methods of managing power supply noise, with the use of decoupling capacitors being the most common technique for suppressing the noise. An in-depth analysis of decap structures including scaling effects is presented in this work with corroborating silicon results. The applicability of various decaps for given design constraints is provided. It is shown that MOS-metal hybrid structures can provide a significant increase in capacitance per unit area compared to traditional structures and will continue to be an important structure as technology continues to scale. Noise suppression by means of current shifting within the clock period of an ALU block is further shown to be an additional method of reducing the minimum voltage observed on its associated supply. A simple, and area and power efficient technique for on-chip supply noise detection is also proposed