Migration from electronics to photonics in multicore processor

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2008.Includes bibliographical references (leaf 54).Twenty - first opportunities for Gigascale Integration will be governed in part by a hierarchy of physical limits on interconnect. Microprocessor performance is now limited by the poor delay and bandwidth performance of the on - chip global wiring layer. This thesis is envisioned as a critical showstopper of electronic industry in the near future. The physical reason behind the interconnect bottleneck is the resistive nature of metals. The introduction of copper in place of aluminum has temporarily improved the interconnect performance, but a more disruptive solution will be required in order to keep the current pace of progress, optical interconnect is an intriguing alternative to metallic wires. Many - core microprocessors will push performance per chip from the 10 gigaflop to the 10 teraflop range in the coming decade. Pin limitations, the energy cost of electrical signaling, and the non - scalability of chip - length global wires are significant bandwidth impediments. Silicon nanophotonic based many core architecture are introduced in order to meet the bandwidth requirements at acceptable power levels.by Zhoujia Xu.M.Eng

Hydrogenated amorphous silicon photonics

Silicon Photonics is quickly proving to be a suitable interconnect technology for meeting the future goals of on-chip bandwidth and low power requirements. However, it is not clear how silicon photonics will be integrated into CMOS chips, particularly microprocessors. The issue of integrating photonic circuits into electronic IC fabrication processes to achieve maximum flexibility and minimize complexity and cost is an important one. In order to maximize usage of chip real estate, it will be advantageous to integrate in three-dimensions. Hydrogenated-amorphous silicon (a-Si:H) is emerging as a promising material for the 3-D integration of silicon photonics for on-chip optical interconnects. In addition, a-Si:H film can be deposited using CMOS compatible low temperature plasma-enhanced chemical vapor deposition (PECVD) process at any point in the fabrication process allowing vertical stacking of optical interconnects. In this thesis we demonstrate a-Si:H as a high performance alternate platform to crystalline silicon, enabling backend integration of optical interconnects in a hybrid photonic-electronic network-on-chip architecture. High quality passive devices are fabricated on a low-loss a-Si:H platform enabling wavelength division multiplexing schemes. We demonstrate a broadband all-optical modulation scheme based on free-carrier absorption effect, which can enable compact electro-optic modulators in a-Si:H. Furthermore, we comprehensively characterize the optical nonlinearities in a-Si:H and observe that a-Si:H exhibits enhanced nonlinearities as compared to crystalline silicon. Based on the enhanced nonlinearities, we demonstrate low-power four-wave mixing in a-Si:H waveguides enabling high-speed all-optical devices in an a-Si:H platform. Finally, we demonstrate a novel data encoding scheme using thermal and all-optical tuning of silicon waveguides, increasing the spectral efficiency in an interconnect link. Looking forward, we shall also discuss some of the challenges that still need to be overcome to realize an integrated a-Si:H based photonic link

On-Chip Optical Interconnection Networks for Multi/Manycore Architectures

The rapid development of multi/manycore technologies offers the opportunity for highly parallel architectures implemented on a single chip. While the first, low-parallelism multicore products have been based on simple interconnection structures (single bus, very simple crossbar), the emerging highly parallel architectures will require complex, limited-degree interconnection networks. This thesis studies this trend according to the general theory of interconnection structures for parallel machines, and investigates some solutions in terms of performance, cost, fault-tolerance, and run-time support to shared-memory and/or message passing programming mechanisms

Architectural Exploration and Design Methodologies of Photonic Interconnection Networks

Photonic technology is becoming an increasingly attractive solution to the problems facing today's electronic chip-scale interconnection networks. Recent progress in silicon photonics research has enabled the demonstration of all the necessary optical building blocks for creating extremely high-bandwidth density and energy-efficient links for on- and off-chip communications. From the feasibility and architecture perspective however, photonics represents a dramatic paradigm shift from traditional electronic network designs due to fundamental differences in how electronics and photonics function and behave. As a result of these differences, new modeling and analysis methods must be employed in order to properly realize a functional photonic chip-scale interconnect design. In this work, we present a methodology for characterizing and modeling fundamental photonic building blocks which can subsequently be combined to form full photonic network architectures. We also describe a set of tools which can be utilized to assess the physical-layer and system-level performance properties of a photonic network. The models and tools are integrated in a novel open-source design and simulation environment called PhoenixSim. Next, we leverage PhoenixSim for the study of chip-scale photonic networks. We examine several photonic networks through the synergistic study of both physical-layer metrics and system-level metrics. This holistic analysis method enables us to provide deeper insight into architecture scalability since it considers insertion loss, crosstalk, and power dissipation. In addition to these novel physical-layer metrics, traditional system-level metrics of bandwidth and latency are also obtained. Lastly, we propose a novel routing architecture known as wavelength-selective spatial routing. This routing architecture is analogous to electronic virtual channels since it enables the transmission of multiple logical optical channels through a single physical plane (i.e. the waveguides). The available wavelength channels are partitioned into separate groups, and each group is routed independently in the network. Each partition is spectrally multiplexed, as opposed to temporally multiplexed in the electronic case. The wavelength-selective spatial routing technique benefits network designers by provider lower contention and increased path diversity