Design, Modeling and Analysis of Non-classical Field Effect Transistors

Transistor scaling following per Moore\u27s Law slows down its pace when entering into nanometer regime where short channel effects (SCEs), including threshold voltage fluctuation, increased leakage current and mobility degradation, become pronounced in the traditional planar silicon MOSFET. In addition, as the demand of diversified functionalities rises, conventional silicon technologies cannot satisfy all non-digital applications requirements because of restrictions that stem from the fundamental material properties. Therefore, novel device materials and structures are desirable to fuel further evolution of semiconductor technologies. In this dissertation, I have proposed innovative device structures and addressed design considerations of those non-classical field effect transistors for digital, analog/RF and power applications with projected benefits. Considering device process difficulties and the dramatic fabrication cost, application-oriented device design and optimization are performed through device physics analysis and TCAD modeling methodology to develop design guidelines utilizing transistor\u27s improved characteristics toward application-specific circuit performance enhancement. Results support proposed device design methodologies that will allow development of novel transistors capable of overcoming limitation of planar nanoscale MOSFETs. In this work, both silicon and III-V compound devices are designed, optimized and characterized for digital and non-digital applications through calibrated 2-D and 3-D TCAD simulation. For digital functionalities, silicon and InGaAs MOSFETs have been investigated. Optimized 3-D silicon-on-insulator (SOI) and body-on-insulator (BOI) FinFETs are simulated to demonstrate their impact on the performance of volatile memory SRAM module with consideration of self-heating effects. Comprehensive simulation results suggest that the current drivability degradation due to increased device temperature is modest for both devices and corresponding digital circuits. However, SOI FinFET is recommended for the design of low voltage operation digital modules because of its faster AC response and better SCEs management than the BOI structure. The FinFET concept is also applied to the non-volatile memory cell at 22 nm technology node for low voltage operation with suppressed SCEs. In addition to the silicon technology, our TCAD estimation based on upper projections show that the InGaAs FinFET, with superior mobility and improved interface conditions, achieve tremendous drive current boost and aggressively suppressed SCEs and thereby a strong contender for low-power high-performance applications over the silicon counterpart. For non-digital functionalities, multi-fin FETs and GaN HEMT have been studied. Mixed-mode simulations along with developed optimization guidelines establish the realistic application potential of underlap design of silicon multi-Fin FETs for analog/RF operation. The device with underlap design shows compromised current drivability but improve analog intrinsic gain and high frequency performance. To investigate the potential of the novel N-polar GaN material, for the first time, I have provided calibrated TCAD modeling of E-mode N-polar GaN single-channel HEMT. In this work, I have also proposed a novel E-mode dual-channel hybrid MIS-HEMT showing greatly enhanced current carrying capability. The impact of GaN layer scaling has been investigated through extensive TCAD simulations and demonstrated techniques for device optimization

A model for programming characteristics of Sonos type flash with high-kappa dielectrics

Silicon Oxide Nitride Oxide Silicon (SONOS) FLASH memories have recently gained a lot of attention due to better retention and scaling opportunities over the conventional Floating Gate FLASH memories. The constant demand for device scaling, to attain higher density, higher performance, and low cost per bit, has posed charge leakage problems. SONOS type devices with high-kappa storage layers and/or high-kappa blocking oxide have been proposed to alleviate the demand for constant tunnel oxide scaling. In comparison to conventional FLASH, these devices operate at lower voltages, exhibit higher programming speeds, comparable retention times, less over-erase problem and better compatibility with low power CMOS logic; The objective of this thesis is to develop a comprehensive model which can be used to obtain the programming characteristics, i.e., shift in threshold voltage vs. program time, for trap-based FLASH memories with high-kappa dielectrics. The proposed model is used to obtain the programming characteristics for SONOS type devices. The results from this model are compared with the experimental results and in general the agreement is good. For SONOS type devices with high-kappa blocking oxides, the density of available nitride traps for charge storage is shown to have a linear dependence with the potential energy difference between the silicon substrate and the nitride storage for different gate biases. The model is also used to get an estimate of available trap energy levels in the nitride layer as a function of applied voltage

Redox-Active Molecules for Novel Nonvolatile Memory Applications

The continuous complementary metal‐oxide‐semiconductor (CMOS) scaling is reaching fundamental limits imposed by the heat dissipation and short‐channel effects, which will finally stop the increase of integration density and the MOSFET performance predicted by Moore’s law. Molecular technology has been aggressively pursued for decades due to its potential impact on future micro‐/nanoelectronics. Molecules, especially redox‐active molecules, have become attractive due to their intrinsic redox behavior, which provides an excellent basis for low‐power, high‐density, and high‐reliability nonvolatile memory applications. This chapter briefly reviews the development of molecular electronics in the application of nonvolatile memory. From the mechanical motion of molecules in the Langmuir‐Blodgett film to new families of redox‐active molecules, memory devices involving hybrid molecular technology have shown advantageous potential in fast speed, low‐power, and high‐density nonvolatile memory and will lead to promising on‐chip memory as well as future portable electronics applications