Low Power Analog-to-Digital Conversion in Millimeter Wave Systems: Impact of Resolution and Bandwidth on Performance

The wide bandwidth and large number of antennas used in millimeter wave systems put a heavy burden on the power consumption at the receiver. In this paper, using an additive quantization noise model, the effect of analog-digital conversion (ADC) resolution and bandwidth on the achievable rate is investigated for a multi-antenna system under a receiver power constraint. Two receiver architectures, analog and digital combining, are compared in terms of performance. Results demonstrate that: (i) For both analog and digital combining, there is a maximum bandwidth beyond which the achievable rate decreases; (ii) Depending on the operating regime of the system, analog combiner may have higher rate but digital combining uses less bandwidth when only ADC power consumption is considered, (iii) digital combining may have higher rate when power consumption of all the components in the receiver front-end are taken into account.Comment: 8 pages, 6 figures, in Proc. of IEEE Information Theory and Applications Workshop, Feb. 201

Limited Feedback in Multiple-Antenna Systems with One-Bit Quantization

Communication systems with low-resolution analog-to-digital-converters (ADCs) can exploit channel state information at the transmitter (CSIT) and receiver. This paper presents initial results on codebook design and performance analysis for limited feedback systems with one-bit ADCs. Different from the high-resolution case, the absolute phase at the receiver is important to align the phase of the received signals when the received signal is sliced by one-bit ADCs. A new codebook design for the beamforming case is proposed that separately quantizes the channel direction and the residual phase.Comment: Asilomar Conference on Signals, Systems, and Computers 201

One-Bit Massive MIMO: Channel Estimation and High-Order Modulations

We investigate the information-theoretic throughout achievable on a fading communication link when the receiver is equipped with one-bit analog-to-digital converters (ADCs). The analysis is conducted for the setting where neither the transmitter nor the receiver have a priori information on the realization of the fading channels. This means that channel-state information needs to be acquired at the receiver on the basis of the one-bit quantized channel outputs. We show that least-squares (LS) channel estimation combined with joint pilot and data processing is capacity achieving in the single-user, single-receive-antenna case. We also investigate the achievable uplink throughput in a massive multiple-input multiple-output system where each element of the antenna array at the receiver base-station feeds a one-bit ADC. We show that LS channel estimation and maximum-ratio combining are sufficient to support both multiuser operation and the use of high-order constellations. This holds in spite of the severe nonlinearity introduced by the one-bit ADCs

5G Millimeter Wave Cellular System Capacity with Fully Digital Beamforming

Due to heavy reliance of millimeter-wave (mmWave) wireless systems on directional links, Beamforming (BF) with high-dimensional arrays is essential for cellular systems in these frequencies. How to perform the array processing in a power efficient manner is a fundamental challenge. Analog and hybrid BF require fewer analog-to-digital converters (ADCs), but can only communicate in a small number of directions at a time,limiting directional search, spatial multiplexing and control signaling. Digital BF enables flexible spatial processing, but must be operated at a low quantization resolution to stay within reasonable power levels. This paper presents a simple additive white Gaussian noise (AWGN) model to assess the effect of low resolution quantization of cellular system capacity. Simulations with this model reveal that at moderate resolutions (3-4 bits per ADC), there is negligible loss in downlink cellular capacity from quantization. In essence, the low-resolution ADCs limit the high SNR, where cellular systems typically do not operate. The findings suggest that low-resolution fully digital BF architectures can be power efficient, offer greatly enhanced control plane functionality and comparable data plane performance to analog BF.Comment: To appear in the Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 201

A Real-Time GPP Software-Defined Radio Testbed for the Physical Layer of Wireless Standards

We present our contribution to the general-purpose-processor-(GPP)-based radio. We describe a baseband software-defined radio testbed for the physical layer of wireless LAN standards. All physical layer functions have been successfully mapped on a Pentium 4 processor that performs these functions in real time. The testbed consists of a transmitter PC with a DAC board and a receiver PC with an ADC board. In our project, we have implemented two different types of standards on this testbed, a continuous-phase-modulation-based standard, Bluetooth, and an OFDM-based standard, HiperLAN/2. However, our testbed can easily be extended to other standards, because the only limitation in our testbed is the maximal channel bandwidth of 20 MHz and of course the processing capabilities of the used PC. The transmitter functions require at most 714 M cycles per second and the receiver functions need 1225 M cycles per second on a Pentium 4 processor. In addition, baseband experiments have been carried out successfully

Design and Validation of a Software Defined Radio Testbed for DVB-T Transmission

This paper describes the design and validation of a Software Defined Radio (SDR) testbed, which can be used for Digital Television transmission using the Digital Video Broadcasting - Terrestrial (DVB-T) standard. In order to generate a DVB-T-compliant signal with low computational complexity, we design an SDR architecture that uses the C/C++ language and exploits multithreading and vectorized instructions. Then, we transmit the generated DVB-T signal in real time, using a common PC equipped with multicore central processing units (CPUs) and a commercially available SDR modem board. The proposed SDR architecture has been validated using fixed TV sets, and portable receivers. Our results show that the proposed SDR architecture for DVB-T transmission is a low-cost low-complexity solution that, in the worst case, only requires less than 22% of CPU load and less than 170 MB of memory usage, on a 3.0 GHz Core i7 processor. In addition, using the same SDR modem board, we design an off-line software receiver that also performs time synchronization and carrier frequency offset estimation and compensation