A heuristic on the rearrangeability of shuffle-exchange networks

The algorithms which control network routing are specific to the network because the algorithms are designed to take advantage of that network\u27s topology. The goodness of a network includes such criteria as a simple routing algorithm and a simple routing algorithm would increase the use of the shuffle-exchange network

Indirect interconnection networks for high performance routers/switches

Routers form the backbone of the Internet; their kernel, structure, andconfiguration (scheduler) of the backplane (or switching fabrics) dominate the routers’performance, scalability, reliability and cost. As higher performance is required with therapid development of the network applications, router’s architecture has also evolvedfrom the shared backplane to switched backplane, which mainly uses the indirectinterconnection networks.The indirect interconnection networks include crossbar, MIN (multistageinterconnection networks) and some other irregular topologies. At present, most oftoday’s routers and switches are implemented on single crossbar with symmetric bufferarchitecture. In the first part of this dissertation, we introduce novel asymmetric bufferarchitecture for the crossbar in which a new port and a local shared bus are added. Wethen evaluate its performance and simulate under different bus arbitration and buffermanagement algorithms. Our studies indicate that we can get great improvement for thethroughput and low drop rate. Thus we could save a lot of expensive link bandwidth anddecrease the probability of congestion for the network.Single crossbar complexity increases at O(N2) in terms of crosspoint number,which become unacceptable for scalability as the port number (N) increases. A delta classself-routing MIN with complexity of O(N×log2N) has been widely used in the ATMswitches. But the reduction of crosspoint number results in considerable internal blocking.A number of scalable methods have been proposed to solve this problem. One of themuses more stages with recirculation architecture to reroute the deflected packets, whichgreatly increase the latency. In the second part of this dissertation, we propose aninterleaved multistage switching fabrics architecture and assess its throughput with ananalytical model and simulations. We compare this novel scheme with some previousparallel architectures and show its benefits. From extensive simulations under differenttraffic patterns and fault models, our interleaved architecture achieves better performancethan its counterpart of single panel fabric. Our interleaved scheme achieves speedups(over the single panel fabric) of 3.4 and 2.25 under uniform and hot-spot traffic patterns,respectively at maximum load (p=1). Moreover, the interleaved fabrics show greattolerance against internal hardware failures

Symmetric rearrangeable networks and algorithms

A class of symmetric rearrangeable nonblocking networks has been considered in this thesis. A particular focus of this thesis is on Benes networks built with 2 x 2 switching elements. Symmetric rearrangeable networks built with larger switching elements have also being considered. New applications of these networks are found in the areas of System on Chip (SoC) and Network on Chip (NoC). Deterministic routing algorithms used in NoC applications suffer low scalability and slow execution time. On the other hand, faster algorithms are blocking and thus limit throughput. This will be an acceptable trade-off for many applications where achieving ”wire speed” on the on-chip network would require extensive optimisation of the attached devices. In this thesis I designed an algorithm that has much lower blocking probabilities than other suboptimal algorithms but a much faster execution time than deterministic routing algorithms. The suboptimal method uses the looping algorithm in its outermost stages and then in the two distinct subnetworks deeper in the switch uses a fast but suboptimal path search method to find available paths. The worst case time complexity of this new routing method is O(NlogN) using a single processor, which matches the best known results reported in the literature. Disruption of the ongoing communications in this class of networks during rearrangements is an open issue. In this thesis I explored a modification of the topology of these networks which gives rise to what is termed as repackable networks. A repackable topology allows rearrangements of paths without intermittently losing connectivity by breaking the existing communication paths momentarily. The repackable network structure proposed in this thesis is efficient in its use of hardware when compared to other proposals in the literature. As most of the deterministic algorithms designed for Benes networks implement a permutation of all inputs to find the routing tags for the requested inputoutput pairs, I proposed a new algorithm that can work for partial permutations. If the network load is defined as ρ, the mean number of active inputs in a partial permutation is, m = ρN, where N is the network size. This new method is based on mapping the network stages into a set of sub-matrices and then determines the routing tags for each pair of requests by populating the cells of the sub-matrices without creating a blocking state. Overall the serial time complexity of this method is O(NlogN) and O(mlogN) where all N inputs are active and with m < N active inputs respectively. With minor modification to the serial algorithm this method can be made to work in the parallel domain. The time complexity of this routing algorithm in a parallel machine with N completely connected processors is O(log^2 N). With m active requests the time complexity goes down to (logmlogN), which is better than the O(log^2 m + logN), reported in the literature for 2^0.5((log^2 -4logN)^0.5-logN)<= ρ <= 1. I also designed multistage symmetric rearrangeable networks using larger switching elements and implement a new routing algorithm for these classes of networks. The network topology and routing algorithms presented in this thesis should allow large scale networks of modest cost, with low setup times and moderate blocking rates, to be constructed. Such switching networks will be required to meet the bandwidth requirements of future communication networks

The Design, modeling and simulation of switching fabrics: For an ATM network switch

The requirements of today\u27s telecommunication systems to support high bandwidth and added flexibility brought about the expansion of (Asynchronous Transfer Mode) ATM as a new method of high-speed data transmission. Various analytical and simulation methods may be used to estimate the performance of ATM switches. Analytical methods considerably limit the range of parameters to be evaluated due to extensive formulae used and time consuming iterations. They are not as effective for large networks because of excessive computations that do not scale linearly with network size. One the other hand, simulation-based methods allow determining a bigger range of performance parameters in a shorter amount of time even for large networks. A simulation model, however, is more elaborate in terms of implementation. Instead of using formulae to obtain results, it has to operate software or hardware modules requiring a certain amount of effort to create. In this work simulation is accomplished by utilizing the ATM library - an object oriented software tool, which uses software chips for building ATM switches. The distinguishing feature of this approach is cut-through routing realized on the bit level abstraction treating ATM protocol data units, called cells, as groups of 424 bits. The arrival events of cells to the system are not instantaneous contrary to commonly used methods of simulation that consider cells as instant messages. The simulation was run for basic multistage interconnection network types with varying source arrival rate and buffer sizes producing a set of graphs of cell delays, throughput, cell loss probability, and queue sizes. The techniques of rearranging and sorting were considered in the simulation. The results indicate that better performance is always achieved by bringing additional stages of elements to the switching system

Optical Interconnections based on Microring Resonators

Projecte fet en col.laboració amb la Facoltà di Ingegneria dell’Informazione. Politecinco de TorinoThe aim of this thesis is to present and analyse optical interconnection architectures based on microring resonators. The trend of meeting large bandwidth and strict latency requirements in both global on-chip and off-chip communication face critical challenges in maintaining a sustainable performance-per-watt. Optical technologies support the immense bandwidth allowed by wavelength division multiplexed (WDM) while could offer a significant power saving switching capabilities. Microring resonators have received considerable attention as promising technologies for realizing photonic integrated circuits. Their small footprint and their capacity for processing high-bandwidth WDM data can lead these devices become the key elements for the switch nodes in next-generation telecommunication networks. This thesis firstly describes the basic principles of operation of a microring resonator defining 1x2 basic switching element (1B-SE). Then, the 2x2 basic SE (2B-SE) based on two 1B-SEs jointly controlled and the new 2x2 mirrored SE (2M-SE) are characterised as atomic building elements for interconnection architectures. The severe asymmetric behaviour presented by those SEs could limit the scalability of classical optical switching fabrics and we aim at balancing the complexity and optical signal level. In a second stage, the well-known switching theory is revised in order to classify the interconnection architectures according to their characteristics when using that SEs as building element. It is applied an exhaustive procedure to obtain the performance of classical Crossbar and Benes structures and of the newly proposed Mirroring and HBC structures. Thereafter, using as a starting point for each analysed structure the characterisation previously obtained, the scalability response of larger switching fabrics is explored. Then we define a construction rule for the new proposed architectures of which we assess the complexity in terms of used microring

Devices and networks for optical switching

This thesis is concerned with some aspects of the application of optics to switching and computing. Two areas are dealt with: the design of switching networks which use optical interconnects, and the development and application of the t-SEED optical logic device. The work on optical interconnects looks at the multistage interconnection network which has been proposed as a hybrid switch using both electronics and optics. It is shown that the architecture can be mapped from one dimensional to two dimensional format, so that the machine makes full use of the space available to the optics. Other mapping rules are described which allow the network to make optimum use of the optical interconnects, and the endpoint is a hybrid optical-electronic machine which should be able to outperform an all-electronic equivalent. The development of the t-SEED optical logic device is described, which is the integration of a phototransistor with a multiple quantum well optical modulator. It is found to be important to have the modulator underneath rather than on top of the transistor to avoid unwanted thyristor action. In order for the transistor to have a high gain the collector must have a low doping level, the exit window in the substrate must be etched all the way to the emitter layer, and the etch must not damage the emitter-base junction. A real optical gain of 1.6 has been obtained, which is higher than has ever been reached before but is not as high as should be possible. Improvements to the device are suggested. A new model of the Fabry-Perot cavity is introduced which helps considerably in the interpretation of experimental measurements made on the quantum well modulators. Also a method of improving the contrast of the multiple quantum well modulator by grading the well widths is proposed which may find application in long wavelength transmission modulators. Some systems which make use of the t-SEED are considered. It is shown that the t-SEED device has the right characteristics for use as a neuron element in the optical implementation of a neural network. A new image processing network for clutter removal in binary images is introduced which uses the t-SEED, and a brief performance analysis suggests that the network may be superior to an all-electronic machine

Optical Interconnections based on Microring Resonators

Projecte fet en col.laboració amb la Facoltà di Ingegneria dell’Informazione. Politecinco de TorinoThe aim of this thesis is to present and analyse optical interconnection architectures based on microring resonators. The trend of meeting large bandwidth and strict latency requirements in both global on-chip and off-chip communication face critical challenges in maintaining a sustainable performance-per-watt. Optical technologies support the immense bandwidth allowed by wavelength division multiplexed (WDM) while could offer a significant power saving switching capabilities. Microring resonators have received considerable attention as promising technologies for realizing photonic integrated circuits. Their small footprint and their capacity for processing high-bandwidth WDM data can lead these devices become the key elements for the switch nodes in next-generation telecommunication networks. This thesis firstly describes the basic principles of operation of a microring resonator defining 1x2 basic switching element (1B-SE). Then, the 2x2 basic SE (2B-SE) based on two 1B-SEs jointly controlled and the new 2x2 mirrored SE (2M-SE) are characterised as atomic building elements for interconnection architectures. The severe asymmetric behaviour presented by those SEs could limit the scalability of classical optical switching fabrics and we aim at balancing the complexity and optical signal level. In a second stage, the well-known switching theory is revised in order to classify the interconnection architectures according to their characteristics when using that SEs as building element. It is applied an exhaustive procedure to obtain the performance of classical Crossbar and Benes structures and of the newly proposed Mirroring and HBC structures. Thereafter, using as a starting point for each analysed structure the characterisation previously obtained, the scalability response of larger switching fabrics is explored. Then we define a construction rule for the new proposed architectures of which we assess the complexity in terms of used microring

Privacy in Bitcoin through decentralized mixers

Dans les crypto-monnaies telles Bitcoin, l’anonymité des utilisateurs peut être compromise de plusieurs façons. Dans ce mémoire, nous effectuons une revue de littérature et une classification des différents protocoles existants pour anonymiser les usagers et analysons leur efficacité. S’appuyant sur certains critères désirables dans de tels protocoles, nous proposons un modèle de mixeur synchrone décentralisé. Nous avons ciblé deux approches qui s’inscrivent dans ce modèle, le plan de transaction et le réseau de transactions, le second étant une contribution originale de ce mémoire. Nous expliquons son fonctionnement puis analysons son efficacité dans le contexte actuel d’utilisation de BitcoinIn cryptocurrencies such as Bitcoin, the anonymity of the users may be compromised in many ways. In this thesis, we review the literature concerning existing protocols used to increase anonymity by a method called mixing and produce a classification for such protocols. We propose a decentralized synchronous N-to-N mixing model that takes into account many considerations of mixers. We address two frameworks within this model, the transaction blueprint and the network of transactions, the second approach being a new contribution. We explain how it functions and analyse its efficiency in the current Bitcoin ecosystem