Економічний менеджмент підприємства і суспільний інноваційний розвиток в умовах ризиків

The knowledge of surface electromyography (SEMG) and the number of applications have increased considerably during the past ten years. However, most methodological developments have taken place locally, resulting in different methodologies among the different groups of users. A specific objective of the European concerted action SENIAM (surface EMG for a non-invasive assessment of muscles) was, besides creating more collaboration among the various European groups, to develop recommendations on sensors, sensor placement, signal processing and modeling. This paper will present the process and the results of the development of the recommendations for the SEMG sensors and sensor placement procedures. Execution of the SENIAM sensor tasks, in the period 1996–1999, has been handled in a number of partly parallel and partly sequential activities. A literature scan was carried out on the use of sensors and sensor placement procedures in European laboratories. In total, 144 peer-reviewed papers were scanned on the applied SEMG sensor properties and sensor placement procedures. This showed a large variability of methodology as well as a rather insufficient description. A special workshop provided an overview on the scientific and clinical knowledge of the effects of sensor properties and sensor placement procedures on the SEMG characteristics. Based on the inventory, the results of the topical workshop and generally accepted state-of-the-art knowledge, a first proposal for sensors and sensor placement procedures was defined. Besides containing a general procedure and recommendations for sensor placement, this was worked out in detail for 27 different muscles. This proposal was evaluated in several European laboratories with respect to technical and practical aspects and also sent to all members of the SENIAM club (>100 members) together with a questionnaire to obtain their comments. Based on this evaluation the final recommendations of SENIAM were made and published (SENIAM 8: European recommendations for surface electromyography, 1999), both as a booklet and as a CD-ROM. In this way a common body of knowledge has been created on SEMG sensors and sensor placement properties as well as practical guidelines for the proper use of SEMG

The space to make mistakes: allocating responsibility and accountability for nursing student-committed medication errors

A medication error committed by a student nurse during a clinical placement often results in the student fearing its potential impact on the patient, unit staff, and the student’s educational journey. Student nurses must navigate two parallel systems during a clinical placement – the educational system and the healthcare system – and there can be confusion about what each requires of the student. Neither of these systems contain clear direction for managing student-committed medication errors and for allocating associated responsibility and accountability. This exploratory mixed methods study examines the process by which responsibility and accountability for a student-committed medication error is allocated and the factors that influence that allocation decision. It describes key features of an ideal allocation process and suggests reasons why the current allocation process often does not meet those requirements. Qualitative data were analyzed through interpretive description and quantitative data were analyzed using descriptive statistics. The results were situated, interpreted, and triangulated within a critical realism philosophical framework. An ideal post-error environment must incorporate a just culture. Since students must navigate both the educational institution and the healthcare facility environments during a clinical placement, a just culture must permeate both. However, students are instead colliding with a post-error environment that they perceive as not meeting key ideals of a just culture: fairness, transparency, minimization of fear, and dedication to learning. Findings of this study can be used to drive change that will better support those who are involved in a post-error process, and decrease the significant inconsistencies that are currently of particular concern

Parallelization of Stochastic Evolution

The complexity involved in VLSI design and its sub-problems has always made them ideal application areas for non-eterministic iterative heuristics. However, the major drawback has been the large runtime involved in reaching acceptable solutions especially in the case of multi-objective optimization problems. Among the acceleration techniques proposed, parallelization of iterative heuristics is a promising one. The motivation for Parallel CAD include faster runtimes, handling of larger problem sizes, and exploration of larger search space. In this work, the development of parallel algorithms for Stochastic Evolution, applied on multi-objective VLSI cell-placement problem is presented. In VLSI circuit design, placement is the process of arranging circuit blocks on a layout. In standard cell design, placement consists of determining optimum positions of all blocks on the layout to satisfy the constraint and improve a number of objectives. The placement objectives in our work are to reduce power dissipation and wire-length while improving performance (timing). The parallelization is achieved on a cluster of workstations interconnected by a low-latency network, by using MPI communication libraries. Circuits from ISCAS-89 are used as benchmarks. Results for parallel Stochastic Evolution are compared with its sequential counterpart as well as with the results achieved by parallel versions of Simulated Annealing as a reference point for both, the quality of solution as well as the execution time. After parallelization, linear and super linear speed-ups were obtained, with no degradation in quality of the solution

Parallelization of Stochastic Evolution

The complexity involved in VLSI design and its sub-problems has always made them ideal application areas for non-eterministic iterative heuristics. However, the major drawback has been the large runtime involved in reaching acceptable solutions especially in the case of multi-objective optimization problems. Among the acceleration techniques proposed, parallelization of iterative heuristics is a promising one. The motivation for Parallel CAD include faster runtimes, handling of larger problem sizes, and exploration of larger search space. In this work, the development of parallel algorithms for Stochastic Evolution, applied on multi-objective VLSI cell-placement problem is presented. In VLSI circuit design, placement is the process of arranging circuit blocks on a layout. In standard cell design, placement consists of determining optimum positions of all blocks on the layout to satisfy the constraint and improve a number of objectives. The placement objectives in our work are to reduce power dissipation and wire-length while improving performance (timing). The parallelization is achieved on a cluster of workstations interconnected by a low-latency network, by using MPI communication libraries. Circuits from ISCAS-89 are used as benchmarks. Results for parallel Stochastic Evolution are compared with its sequential counterpart as well as with the results achieved by parallel versions of Simulated Annealing as a reference point for both, the quality of solution as well as the execution time. After parallelization, linear and super linear speed-ups were obtained, with no degradation in quality of the solution

Green Placement – An Innovative Concept & Strategy in Campus Placement Model

Campus Placements as we know today is a process involving interview of college students by recruiting companies utilizing institutional resources towards candidate job selection. The same campus placements which are being traditionally conducted by the arrival of HR Team to campus, their pre-placement talk about company and job description with the gradual interview rounds is slowly beginning to shift its perspectives towards a more greener stature. Especially now with the application of modern technology in hiring practices like E-Recruiting or On-line Recruitment, the entire campus recruitment process is also poised to leap towards a rapid change. Therefore, this research paper aims to construct an ideal strategy towards implementing campus placement process in parallel lines of E-Recruiting as well but with a more environment-friendly approach. This on-line campus placement process termed as 'Green Placements' will thrive as a conceptual model focused on to reduce resource wastages, save water, time, space, electricity by preserving the surrounding environment clean and green whilst the placement activity is being conducted at the college

Green Placement – An Innovative Concept & Strategy in Campus Placement Model

Campus Placements as we know today is a process involving interview of college students by recruiting companies utilizing institutional resources towards candidate job selection. The same campus placements which are being traditionally conducted by the arrival of HR Team to campus, their pre-placement talk about company and job description with the gradual interview rounds is slowly beginning to shift its perspectives towards a more greener stature. Especially now with the application of modern technology in hiring practices like E-Recruiting or On-line Recruitment, the entire campus recruitment process is also poised to leap towards a rapid change. Therefore, this research paper aims to construct an ideal strategy towards implementing campus placement process in parallel lines of E-Recruiting as well but with a more environment-friendly approach. This on-line campus placement process termed as 'Green Placements' will thrive as a conceptual model focused on to reduce resource wastages, save water, time, space, electricity by preserving the surrounding environment clean and green whilst the placement activity is being conducted at the college

Parallelization of Iterative Heuristic for Performance-Driven Low-Power VLSI Standard Cell Placement.

The complexity involved in VLSI design and its sub-problems has always made them ideal application areas for non-deterministic iterative heuristics. However, the major drawback has been the large runtime involved in reaching acceptable solutions especially in the case of multi-objective optimization problems. Among the acceleration techniques proposed, parallelization of these heuristics is one promising alternate. The motivation for Parallel CAD include faster runtimes, handling of larger problem sizes, and exploration of larger search space. In this work, the development of parallel algorithms for Tabu Search, applied on multi-objective VLSI cell-placement problem is presented. In VLSI circuit design, placement is the process of arranging circuit blocks on a layout. In standard cell design, placement consists of determining optimum positions of all blocks on the layout to satisfy the constraint and improve a number of objectives. The placement objectives in our work are to reduce power dissipation and wire-length while improving performance (timing). The parallelization is achieved on a cluster of workstations interconnected by a low-latency network (ethernet), by using Message Passing Interface (MPI) communication libraries. Circuits from ISCAS-89 are used as benchmarks. Results for parallel Tabu Search are compared with its sequential counterpart as a reference point for both, the quality of solution as well as the execution time

Parallelization of Iterative Heuristic for Performance-Driven Low-Power VLSI Standard Cell Placement.

The complexity involved in VLSI design and its sub-problems has always made them ideal application areas for non-deterministic iterative heuristics. However, the major drawback has been the large runtime involved in reaching acceptable solutions especially in the case of multi-objective optimization problems. Among the acceleration techniques proposed, parallelization of these heuristics is one promising alternate. The motivation for Parallel CAD include faster runtimes, handling of larger problem sizes, and exploration of larger search space. In this work, the development of parallel algorithms for Tabu Search, applied on multi-objective VLSI cell-placement problem is presented. In VLSI circuit design, placement is the process of arranging circuit blocks on a layout. In standard cell design, placement consists of determining optimum positions of all blocks on the layout to satisfy the constraint and improve a number of objectives. The placement objectives in our work are to reduce power dissipation and wire-length while improving performance (timing). The parallelization is achieved on a cluster of workstations interconnected by a low-latency network (ethernet), by using Message Passing Interface (MPI) communication libraries. Circuits from ISCAS-89 are used as benchmarks. Results for parallel Tabu Search are compared with its sequential counterpart as a reference point for both, the quality of solution as well as the execution time