4 research outputs found
Biconditional Binary Decision Diagrams: A Novel Canonical Logic Representation Form
In this paper, we present biconditional binary deci- sion diagrams (BBDDs), a novel canonical representation form for Boolean functions. BBDDs are binary decision diagrams where the branching condition, and its associated logic expansion, is biconditional on two variables. Empowered by reduction and ordering rules, BBDDs are remarkably compact and unique for a Boolean function. The interest of such representation form in modern electronic design automation (EDA) is twofold. On the one hand, BBDDs improve the efficiency of traditional EDA tasks based on decision diagrams, especially for arithmetic intensive designs. On the other hand, BBDDs represent the natural and native design abstraction for emerging technologies where the circuit primitive is a comparator, rather than a simple switch. We provide, in this paper, a solid ground for BBDDs by studying their underlying theory and manipulation properties. Thanks to an efficient BBDD software package implementation, we validate 1) speed-up in traditional decision diagrams applications with up to 4.4 gain with respect to other DDs, and 2) improved synthesis of circuits in emerging technologies, with about 32% shorter critical path than state-of-art synthesis techniques
Approximate logic circuits: Theory and applications
CMOS technology scaling, the process of shrinking transistor dimensions based
on Moore's law, has been the thrust behind increasingly powerful integrated circuits
for over half a century. As dimensions are scaled to few tens of nanometers, process
and environmental variations can significantly alter transistor characteristics, thus
degrading reliability and reducing performance gains in CMOS designs with technology
scaling. Although design solutions proposed in recent years to improve reliability
of CMOS designs are power-efficient, the performance penalty associated with these
solutions further reduces performance gains with technology scaling, and hence these
solutions are not well-suited for high-performance designs.
This thesis proposes approximate logic circuits as a new logic synthesis paradigm
for reliable, high-performance computing systems. Given a specification, an approximate
logic circuit is functionally equivalent to the given specification for a "significant"
portion of the input space, but has a smaller delay and power as compared to a
circuit implementation of the original specification. This contributions of this thesis
include (i) a general theory of approximation and efficient algorithms for automated
synthesis of approximations for unrestricted random logic circuits, (ii) logic design solutions
based on approximate circuits to improve reliability of designs with negligible
performance penalty, and (iii) efficient decomposition algorithms based on approxiiii
mate circuits to improve performance of designs during logic synthesis. This thesis
concludes with other potential applications of approximate circuits and identifies. open
problems in logic decomposition and approximate circuit synthesis
Probabilistic Inference in Piecewise Graphical Models
In many applications of probabilistic inference the models
contain piecewise densities that are differentiable except at
partition boundaries. For instance, (1) some models may
intrinsically have finite support, being constrained to some
regions; (2) arbitrary density functions may be approximated by
mixtures of piecewise functions such as piecewise polynomials or
piecewise exponentials; (3) distributions derived from other
distributions (via random variable transformations) may be highly
piecewise; (4) in applications of Bayesian inference such as
Bayesian discrete classification and preference learning, the
likelihood functions may be piecewise; (5) context-specific
conditional probability density functions (tree-CPDs) are
intrinsically piecewise; (6) influence diagrams (generalizations
of Bayesian networks in which along with probabilistic inference,
decision making problems are modeled) are in many applications
piecewise; (7) in probabilistic programming, conditional
statements lead to piecewise models. As we will show, exact
inference on piecewise models is not often scalable (if
applicable) and the performance of the existing approximate
inference techniques on such models is usually quite poor.
This thesis fills this gap by presenting scalable and accurate
algorithms for inference in piecewise probabilistic graphical
models. Our first contribution is to present a variation of Gibbs
sampling algorithm that achieves an exponential sampling speedup
on a large class of models (including Bayesian models with
piecewise likelihood functions). As a second contribution, we
show that for a large range of models, the time-consuming Gibbs
sampling computations that are traditionally carried out per
sample, can be computed symbolically, once and prior to the
sampling process. Among many potential applications, the
resulting symbolic Gibbs sampler can be used for fully automated
reasoning in the presence of deterministic constraints among
random variables. As a third contribution, we are motivated by
the behavior of Hamiltonian dynamics in optics —in particular,
the reflection and refraction of light on the refractive
surfaces— to present a new Hamiltonian Monte Carlo method that
demonstrates a significantly improved performance on piecewise
models.
Hopefully, the present work represents a step towards scalable
and accurate inference in an important class of probabilistic
models that has largely been overlooked in the literature
New Data Structures and Algorithms for Logic Synthesis and Verification
The strong interaction between Electronic Design Automation (EDA) tools and Complementary Metal-Oxide Semiconductor (CMOS) technology contributed substantially to the advancement of modern digital electronics. The continuous downscaling of CMOS Field Effect Transistor (FET) dimensions enabled the semiconductor industry to fabricate digital systems with higher circuit density at reduced costs. To keep pace with technology, EDA tools are challenged to handle both digital designs with growing functionality and device models of increasing complexity. Nevertheless, whereas the downscaling of CMOS technology is requiring more complex physical design models, the logic abstraction of a transistor as a switch has not changed even with the introduction of 3D FinFET technology. As a consequence, modern EDA tools are fine tuned for CMOS technology and the underlying design methodologies are based on CMOS logic primitives, i.e., negative unate logic functions. While it is clear that CMOS logic primitives will be the ultimate building blocks for digital systems in the next ten years, no evidence is provided that CMOS logic primitives are also the optimal basis for EDA software. In EDA, the efficiency of methods and tools is measured by different metrics such as (i) the result quality, for example the performance of a digital circuit, (ii) the runtime and (iii) the memory footprint on the host computer. With the aim to optimize these metrics, the accordance to a specific logic model is no longer important. Indeed, the key to the success of an EDA technique is the expressive power of the logic primitives handling and solving the problem, which determines the capability to reach better metrics. In this thesis, we investigate new logic primitives for electronic design automation tools. We improve the efficiency of logic representation, manipulation and optimization tasks by taking advantage of majority and biconditional logic primitives. We develop synthesis tools exploiting the majority and biconditional expressiveness. Our tools show strong results as compared to state-of-the-art academic and commercial synthesis tools. Indeed, we produce the best results for several public benchmarks. On top of the enhanced synthesis power, our methods are the natural and native logic abstraction for circuit design in emerging nanotechnologies, where majority and biconditional logic are the primitive gates for physical implementation. We accelerate formal methods by (i) studying properties of logic circuits and (ii) developing new frameworks for logic reasoning engines. We prove non-trivial dualities for the property checking problem in logic circuits. Our findings enable sensible speed-ups in solving circuit satisfiability. We develop an alternative Boolean satisfiability framework based on majority functions. We prove that the general problem is still intractable but we show practical restrictions that can be solved efficiently. Finally, we focus on reversible logic where we propose a new equivalence checking approach. We exploit the invertibility of computation and the functionality of reversible gates in the formulation of the problem. This enables one order of magnitude speed up, as compared to the state-of-the-art solution. We argue that new approaches to solve EDA problems are necessary, as we have reached a point of technology where keeping pace with design goals is tougher than ever