3,305 research outputs found
Intermediate problems in modular circuits satisfiability
In arXiv:1710.08163 a generalization of Boolean circuits to arbitrary finite
algebras had been introduced and applied to sketch P versus NP-complete
borderline for circuits satisfiability over algebras from congruence modular
varieties. However the problem for nilpotent (which had not been shown to be
NP-hard) but not supernilpotent algebras (which had been shown to be polynomial
time) remained open.
In this paper we provide a broad class of examples, lying in this grey area,
and show that, under the Exponential Time Hypothesis and Strong Exponential
Size Hypothesis (saying that Boolean circuits need exponentially many modular
counting gates to produce boolean conjunctions of any arity), satisfiability
over these algebras have intermediate complexity between and , where measures how much a nilpotent algebra
fails to be supernilpotent. We also sketch how these examples could be used as
paradigms to fill the nilpotent versus supernilpotent gap in general.
Our examples are striking in view of the natural strong connections between
circuits satisfiability and Constraint Satisfaction Problem for which the
dichotomy had been shown by Bulatov and Zhuk
A Survey of Satisfiability Modulo Theory
Satisfiability modulo theory (SMT) consists in testing the satisfiability of
first-order formulas over linear integer or real arithmetic, or other theories.
In this survey, we explain the combination of propositional satisfiability and
decision procedures for conjunctions known as DPLL(T), and the alternative
"natural domain" approaches. We also cover quantifiers, Craig interpolants,
polynomial arithmetic, and how SMT solvers are used in automated software
analysis.Comment: Computer Algebra in Scientific Computing, Sep 2016, Bucharest,
Romania. 201
Generating and Searching Families of FFT Algorithms
A fundamental question of longstanding theoretical interest is to prove the
lowest exact count of real additions and multiplications required to compute a
power-of-two discrete Fourier transform (DFT). For 35 years the split-radix
algorithm held the record by requiring just 4n log n - 6n + 8 arithmetic
operations on real numbers for a size-n DFT, and was widely believed to be the
best possible. Recent work by Van Buskirk et al. demonstrated improvements to
the split-radix operation count by using multiplier coefficients or "twiddle
factors" that are not n-th roots of unity for a size-n DFT. This paper presents
a Boolean Satisfiability-based proof of the lowest operation count for certain
classes of DFT algorithms. First, we present a novel way to choose new yet
valid twiddle factors for the nodes in flowgraphs generated by common
power-of-two fast Fourier transform algorithms, FFTs. With this new technique,
we can generate a large family of FFTs realizable by a fixed flowgraph. This
solution space of FFTs is cast as a Boolean Satisfiability problem, and a
modern Satisfiability Modulo Theory solver is applied to search for FFTs
requiring the fewest arithmetic operations. Surprisingly, we find that there
are FFTs requiring fewer operations than the split-radix even when all twiddle
factors are n-th roots of unity.Comment: Preprint submitted on March 28, 2011, to the Journal on
Satisfiability, Boolean Modeling and Computatio
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