On a lower bound for the redundancy of reliable networks with noisy gates

Cover title.Includes bibliographical references (p. 8).Research supported by the NSF. ECS-8552419 Research supported by Bellcore, Inc. and Du Pont. Research supported by the ARO. DAAL03-86-K-0171Nicholas Pippenger, George D. Stamoulis, and John N. Tsitsiklis

On a Lower Bound for the Redundancy of Reliable Networks with Noisy Gates

A proof is provided that a logarithmic redundancy factor is necessary for the reliable computation of the parity function by means of a network with noisy gates. This result was first stated by R.L. Dobrushin and S.I. Ortyukov (1977). However, the authors believe that the analysis given by Dobrushin and Ortyukov is not entirely correct. The authors establish the result by following the same steps and by replacing the questionable part of their analysis with entirely new arguments

Defect tolerance: fundamental limits and examples

This paper addresses the problem of adding redundancy to a collection of physical objects so that the overall system is more robust to failures. In contrast to its information counterpart, which can exploit parity to protect multiple information symbols from a single erasure, physical redundancy can only be realized through duplication and substitution of objects. We propose a bipartite graph model for designing defect-tolerant systems, in which the defective objects are replaced by the judiciously connected redundant objects. The fundamental limits of this model are characterized under various asymptotic settings and both asymptotic and finite-size systems that approach these limits are constructed. Among other results, we show that the simple modular redundancy is in general suboptimal. As we develop, this combinatorial problem of defect tolerant system design has a natural interpretation as one of graph coloring, and the analysis is significantly different from that traditionally used in information redundancy for error-control codes.©201

Energy-efficient circuit design

We initiate the theoretical investigation of energy-efficient circuit design. We assume that the circuit design speci-fies the circuit layout as well as the supply voltages for the gates. To obtain maximum energy efficiency, the circuit de-sign must balance the conflicting demands of minimizing the energy used per gate, and minimizing the number of gates in the circuit; If the energy supplied to the gates is small, then functional failures are likely, necessitating a circuit layout that is more fault-tolerant, and thus that has more gates. By leveraging previous work on fault-tolerant circuit design, we show general upper and lower bounds on the amount of energy required by a circuit to compute a given rela-tion. We show that some circuits would be asymptotically more energy-efficient if heterogeneous supply voltages were allowed, and show that for some circuits the most energy-efficient supply voltages are homogeneous over all gates