Combined on-line lifetime-energy optimization for asymmetric multicores

In this paper we present an architectural and on-line resource management solution to optimize lifetime reliability of asymmetric multicores while minimizing the system energy consumption, targeting both single nodes (multicores) as well as multiple ones (cluster of multicores). The solution exploits the different characteristics of the computing resources to achieve the desired performance while optimizing the lifetime/energy trade-off. The experimental results show that a combined optimization of energy and lifetime allows for achieving an extended lifetime (similar to the one pursued by lifetime-only optimization solutions) with a marginal energy consumption detriment (less than 2%) with respect to energy-aware but aging-unaware systems

Aging-Aware Request Scheduling for Non-Volatile Main Memory

Modern computing systems are embracing non-volatile memory (NVM) to implement high-capacity and low-cost main memory. Elevated operating voltages of NVM accelerate the aging of CMOS transistors in the peripheral circuitry of each memory bank. Aggressive device scaling increases power density and temperature, which further accelerates aging, challenging the reliable operation of NVM-based main memory. We propose HEBE, an architectural technique to mitigate the circuit aging-related problems of NVM-based main memory. HEBE is built on three contributions. First, we propose a new analytical model that can dynamically track the aging in the peripheral circuitry of each memory bank based on the bank's utilization. Second, we develop an intelligent memory request scheduler that exploits this aging model at run time to de-stress the peripheral circuitry of a memory bank only when its aging exceeds a critical threshold. Third, we introduce an isolation transistor to decouple parts of a peripheral circuit operating at different voltages, allowing the decoupled logic blocks to undergo long-latency de-stress operations independently and off the critical path of memory read and write accesses, improving performance. We evaluate HEBE with workloads from the SPEC CPU2017 Benchmark suite. Our results show that HEBE significantly improves both performance and lifetime of NVM-based main memory.Comment: To appear in ASP-DAC 202

Lifetime reliability of multi-core systems: modeling and applications.

Huang, Lin.Thesis (M.Phil.)--Chinese University of Hong Kong, 2011.Includes bibliographical references (leaves 218-232).Abstracts in English and Chinese.Abstract --- p.iAcknowledgement --- p.ivChapter 1 --- Introduction --- p.1Chapter 1.1 --- Preface --- p.1Chapter 1.2 --- Background --- p.5Chapter 1.3 --- Contributions --- p.6Chapter 1.3.1 --- Lifetime Reliability Modeling --- p.6Chapter 1.3.2 --- Simulation Framework --- p.7Chapter 1.3.3 --- Applications --- p.9Chapter 1.4 --- Thesis Outline --- p.10Chapter I --- Modeling --- p.12Chapter 2 --- Lifetime Reliability Modeling --- p.13Chapter 2.1 --- Notation --- p.13Chapter 2.2 --- Assumption --- p.16Chapter 2.3 --- Introduction --- p.16Chapter 2.4 --- Related Work --- p.19Chapter 2.5 --- System Model --- p.21Chapter 2.5.1 --- Reliability of A Surviving Component --- p.22Chapter 2.5.2 --- Reliability of a Hybrid k-out-of-n:G System --- p.26Chapter 2.6 --- Special Cases --- p.31Chapter 2.6.1 --- Case I: Gracefully Degrading System --- p.31Chapter 2.6.2 --- Case II: Standby Redundant System --- p.33Chapter 2.6.3 --- Case III: l-out-of-3:G System with --- p.34Chapter 2.7 --- Numerical Results --- p.37Chapter 2.7.1 --- Experimental Setup --- p.37Chapter 2.7.2 --- Experimental Results and Discussion --- p.40Chapter 2.8 --- Conclusion --- p.43Chapter 2.9 --- Appendix --- p.44Chapter II --- Simulation Framework --- p.47Chapter 3 --- AgeSim: A Simulation Framework --- p.48Chapter 3.1 --- Introduction --- p.48Chapter 3.2 --- Preliminaries and Motivation --- p.51Chapter 3.2.1 --- Prior Work on Lifetime Reliability Analysis of Processor- Based Systems --- p.51Chapter 3.2.2 --- Motivation of This Work --- p.53Chapter 3.3 --- The Proposed Framework --- p.54Chapter 3.4 --- Aging Rate Calculation --- p.57Chapter 3.4.1 --- Lifetime Reliability Calculation --- p.58Chapter 3.4.2 --- Aging Rate Extraction --- p.60Chapter 3.4.3 --- Discussion on Representative Workload --- p.63Chapter 3.4.4 --- Numerical Validation --- p.65Chapter 3.4.5 --- Miscellaneous --- p.66Chapter 3.5 --- Lifetime Reliability Model for MPSoCs with Redundancy --- p.68Chapter 3.6 --- Case Studies --- p.70Chapter 3.6.1 --- Dynamic Voltage and Frequency Scaling --- p.71Chapter 3.6.2 --- Burst Task Arrival --- p.75Chapter 3.6.3 --- Task Allocation on Multi-Core Processors --- p.77Chapter 3.6.4 --- Timeout Policy on Multi-Core Processors with Gracefully Degrading Redundancy --- p.78Chapter 3.7 --- Conclusion --- p.79Chapter 4 --- Evaluating Redundancy Schemes --- p.83Chapter 4.1 --- Introduction --- p.83Chapter 4.2 --- Preliminaries and Motivation --- p.85Chapter 4.2.1 --- Failure Mechanisms --- p.85Chapter 4.2.2 --- Related Work and Motivation --- p.86Chapter 4.3 --- Proposed Analytical Model for the Lifetime Reliability of Proces- sor Cores --- p.88Chapter 4.3.1 --- "Impact of Temperature, Voltage, and Frequency" --- p.88Chapter 4.3.2 --- Impact of Workloads --- p.92Chapter 4.4 --- Lifetime Reliability Analysis for Multi-core Processors with Vari- ous Redundancy Schemes --- p.95Chapter 4.4.1 --- Gracefully Degrading System (GDS) --- p.95Chapter 4.4.2 --- Processor Rotation System (PRS) --- p.97Chapter 4.4.3 --- Standby Redundant System (SRS) --- p.98Chapter 4.4.4 --- Extension to Heterogeneous System --- p.99Chapter 4.5 --- Experimental Methodology --- p.101Chapter 4.5.1 --- Workload Description --- p.102Chapter 4.5.2 --- Temperature Distribution Extraction --- p.102Chapter 4.5.3 --- Reliability Factors --- p.103Chapter 4.6 --- Results and Discussions --- p.103Chapter 4.6.1 --- Wear-out Rate Computation --- p.103Chapter 4.6.2 --- Comparison on Lifetime Reliability --- p.105Chapter 4.6.3 --- Comparison on Performance --- p.110Chapter 4.6.4 --- Comparison on Expected Computation Amount --- p.112Chapter 4.7 --- Conclusion --- p.118Chapter III --- Applications --- p.119Chapter 5 --- Task Allocation and Scheduling for MPSoCs --- p.120Chapter 5.1 --- Introduction --- p.120Chapter 5.2 --- Prior Work and Motivation --- p.122Chapter 5.2.1 --- IC Lifetime Reliability --- p.122Chapter 5.2.2 --- Task Allocation and Scheduling for MPSoC Designs --- p.124Chapter 5.3 --- Proposed Task Allocation and Scheduling Strategy --- p.126Chapter 5.3.1 --- Problem Definition --- p.126Chapter 5.3.2 --- Solution Representation --- p.128Chapter 5.3.3 --- Cost Function --- p.129Chapter 5.3.4 --- Simulated Annealing Process --- p.130Chapter 5.4 --- Lifetime Reliability Computation for MPSoC Embedded Systems --- p.133Chapter 5.5 --- Efficient MPSoC Lifetime Approximation --- p.138Chapter 5.5.1 --- Speedup Technique I - Multiple Periods --- p.139Chapter 5.5.2 --- Speedup Technique II - Steady Temperature --- p.139Chapter 5.5.3 --- Speedup Technique III - Temperature Pre- calculation --- p.140Chapter 5.5.4 --- Speedup Technique IV - Time Slot Quantity Control --- p.144Chapter 5.6 --- Experimental Results --- p.144Chapter 5.6.1 --- Experimental Setup --- p.144Chapter 5.6.2 --- Results and Discussion --- p.146Chapter 5.7 --- Conclusion and Future Work --- p.152Chapter 6 --- Energy-Efficient Task Allocation and Scheduling --- p.154Chapter 6.1 --- Introduction --- p.154Chapter 6.2 --- Preliminaries and Problem Formulation --- p.157Chapter 6.2.1 --- Related Work --- p.157Chapter 6.2.2 --- Problem Formulation --- p.159Chapter 6.3 --- Analytical Models --- p.160Chapter 6.3.1 --- Performance and Energy Models for DVS-Enabled Pro- cessors --- p.160Chapter 6.3.2 --- Lifetime Reliability Model --- p.163Chapter 6.4 --- Proposed Algorithm for Single-Mode Embedded Systems --- p.165Chapter 6.4.1 --- Task Allocation and Scheduling --- p.165Chapter 6.4.2 --- Voltage Assignment for DVS-Enabled Processors --- p.168Chapter 6.5 --- Proposed Algorithm for Multi-Mode Embedded Systems --- p.169Chapter 6.5.1 --- Feasible Solution Set --- p.169Chapter 6.5.2 --- Searching Procedure for a Single Mode --- p.171Chapter 6.5.3 --- Feasible Solution Set Identification --- p.171Chapter 6.5.4 --- Multi-Mode Combination --- p.177Chapter 6.6 --- Experimental Results --- p.178Chapter 6.6.1 --- Experimental Setup --- p.178Chapter 6.6.2 --- Case Study --- p.180Chapter 6.6.3 --- Sensitivity Analysis --- p.181Chapter 6.6.4 --- Extensive Results --- p.183Chapter 6.7 --- Conclusion --- p.185Chapter 7 --- Customer-Aware Task Allocation and Scheduling --- p.186Chapter 7.1 --- Introduction --- p.186Chapter 7.2 --- Prior Work and Problem Formulation --- p.188Chapter 7.2.1 --- Related Work and Motivation --- p.188Chapter 7.2.2 --- Problem Formulation --- p.191Chapter 7.3 --- Proposed Design-Stage Task Allocation and Scheduling --- p.192Chapter 7.3.1 --- Solution Representation and Moves --- p.193Chapter 7.3.2 --- Cost Function --- p.196Chapter 7.3.3 --- Impact of DVFS --- p.198Chapter 7.4 --- Proposed Algorithm for Online Adjustment --- p.200Chapter 7.4.1 --- Reliability Requirement for Online Adjustment --- p.201Chapter 7.4.2 --- Analytical Model --- p.203Chapter 7.4.3 --- Overall Flow --- p.204Chapter 7.5 --- Experimental Results --- p.205Chapter 7.5.1 --- Experimental Setup --- p.205Chapter 7.5.2 --- Results and Discussion --- p.207Chapter 7.6 --- Conclusion --- p.211Chapter 7.7 --- Appendix --- p.211Chapter 8 --- Conclusion and Future Work --- p.214Chapter 8.1 --- Conclusion --- p.214Chapter 8.2 --- Future Work --- p.215Bibliography --- p.23