Efficient design of CMOS TSC checkers

This paper considers the design of an efficient, robustly testable, CMOS Totally Self-Checking (TSC) Checker for k-out-of-2k codes. Most existing implementations use primitive gates and assume the single stuck-at fault model. The self-testing property has been found to fail for CMOS TSC checkers under the stuck-open fault model due to timing skews and arbitrary delays in the circuit. A new four level design using CMOS primitive gates (NAND, NOR, INVERTERS) is presented. This design retains its properties under the stuck-open fault model. Additionally, this method offers an impressive reduction (greater than 70 percent) in gate count, gate inputs, and test set size when compared to the existing method. This implementation is easily realizable and is based on Anderson's technique. A thorough comparative study has been made on the proposed implementation and Kundu's implementation and the results indicate that the proposed one is better than Kundu's in all respects for k-out-of-2k codes

Design of CMOS PSCD circuits and checkers for stuck-at and stuck-on faults

[[abstract]]We present in this paper an approach to designing partially strongly code-disjoint (PSCD) CMOS circuits and checkers, considering transistor stuck-on faults in addition to gate-level stuck-at faults. Our design-for-testability (DFT) technique requires only a small number of extra transistors for monitoring abnormal static currents, coupled with a simple clocking scheme, to detect the stuck-on faults concurrently. The DFT circuitry not only can detect the faults in the functional circuit but also can detect or tolerate faults in itself, making it a good candidate for checker design. Switch and circuit level simulations were performed on a sample circuit, and a sample 4-out-of-8 code checker chip using the proposed technique has been designed, fabricated, and tested, showing the correctness of the method. Performance penalty is reduced by a novel BiCMOS checker circuit.[[fileno]]2030108010057[[department]]電機工程學

A Generic Dual Core Architecture with Error Containment

The dual core strategy allows to construct a fail-silent processor from two instances (master/checker) of any arbitrary standard processor. Its main drawbacks are its vulnerability with respect to common mode failures and the existence of residual single points of failure. In this paper we propose a generic frame that systematically eliminates these drawbacks. First, we employ temporal redundancy to cope with common mode failures. Unlike similar approaches we can ensure error containment even if -- as a result of the temporal redundancy -- the comparison by the checker core is delayed. We attain this by introducing a specific delay element for outgoing data. Second, we perform a systematic analysis of potential single points of failure and eliminate these by careful layout, self-checking circuits and similar methods. We finally validate our approach by means of exhaustive fault injection experiments. The results indicate a 100% self-checking coverage for stuck-at faults and complete error containment. Since the proposed framework has been kept generic in the sense that the individual standard processor cores are treated as black boxes, these results are valid independent of the core actually used

NASA Space Engineering Research Center Symposium on VLSI Design

The NASA Space Engineering Research Center (SERC) is proud to offer, at its second symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories and the electronics industry. These featured speakers share insights into next generation advances that will serve as a basis for future VLSI design. Questions of reliability in the space environment along with new directions in CAD and design are addressed by the featured speakers