Wideband Power Spectrum Sensing: a Fast Practical Solution for Nyquist Folding Receiver

The limited availability of spectrum resources has been growing into a critical problem in wireless communications, remote sensing, and electronic surveillance, etc. To address the high-speed sampling bottleneck of wideband spectrum sensing, a fast and practical solution of power spectrum estimation for Nyquist folding receiver (NYFR) is proposed in this paper. The NYFR architectures is can theoretically achieve the full-band signal sensing with a hundred percent of probability of intercept. But the existing algorithm is difficult to realize in real-time due to its high complexity and complicated calculations. By exploring the sub-sampling principle inherent in NYFR, a computationally efficient method is introduced with compressive covariance sensing. That can be efficient implemented via only the non-uniform fast Fourier transform, fast Fourier transform, and some simple multiplication operations. Meanwhile, the state-of-the-art power spectrum reconstruction model for NYFR of time-domain and frequency-domain is constructed in this paper as a comparison. Furthermore, the computational complexity of the proposed method scales linearly with the Nyquist-rate sampled number of samples and the sparsity of spectrum occupancy. Simulation results and discussion demonstrate that the low complexity in sampling and computation is a more practical solution to meet the real-time wideband spectrum sensing applications

Comprehensive survey on quality of service provisioning approaches in cognitive radio networks : part one

Much interest in Cognitive Radio Networks (CRNs) has been raised recently by enabling unlicensed (secondary) users to utilize the unused portions of the licensed spectrum. CRN utilization of residual spectrum bands of Primary (licensed) Networks (PNs) must avoid harmful interference to the users of PNs and other overlapping CRNs. The coexisting of CRNs depends on four components: Spectrum Sensing, Spectrum Decision, Spectrum Sharing, and Spectrum Mobility. Various approaches have been proposed to improve Quality of Service (QoS) provisioning in CRNs within fluctuating spectrum availability. However, CRN implementation poses many technical challenges due to a sporadic usage of licensed spectrum bands, which will be increased after deploying CRNs. Unlike traditional surveys of CRNs, this paper addresses QoS provisioning approaches of CRN components and provides an up-to-date comprehensive survey of the recent improvement in these approaches. Major features of the open research challenges of each approach are investigated. Due to the extensive nature of the topic, this paper is the first part of the survey which investigates QoS approaches on spectrum sensing and decision components respectively. The remaining approaches of spectrum sharing and mobility components will be investigated in the next part

Design and debugging of multi-step analog to digital converters

With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. The trend of increasing integration level for integrated circuits has forced the A/D converter interface to reside on the same silicon in complex mixed-signal ICs containing mostly digital blocks for DSP and control. However, specifications of the converters in various applications emphasize high dynamic range and low spurious spectral performance. It is nontrivial to achieve this level of linearity in a monolithic environment where post-fabrication component trimming or calibration is cumbersome to implement for certain applications or/and for cost and manufacturability reasons. Additionally, as CMOS integrated circuits are accomplishing unprecedented integration levels, potential problems associated with device scaling – the short-channel effects – are also looming large as technology strides into the deep-submicron regime. The A/D conversion process involves sampling the applied analog input signal and quantizing it to its digital representation by comparing it to reference voltages before further signal processing in subsequent digital systems. Depending on how these functions are combined, different A/D converter architectures can be implemented with different requirements on each function. Practical realizations show the trend that to a first order, converter power is directly proportional to sampling rate. However, power dissipation required becomes nonlinear as the speed capabilities of a process technology are pushed to the limit. Pipeline and two-step/multi-step converters tend to be the most efficient at achieving a given resolution and sampling rate specification. This thesis is in a sense unique work as it covers the whole spectrum of design, test, debugging and calibration of multi-step A/D converters; it incorporates development of circuit techniques and algorithms to enhance the resolution and attainable sample rate of an A/D converter and to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover and compensate for the errors continuously. The power proficiency for high resolution of multi-step converter by combining parallelism and calibration and exploiting low-voltage circuit techniques is demonstrated with a 1.8 V, 12-bit, 80 MS/s, 100 mW analog to-digital converter fabricated in five-metal layers 0.18-µm CMOS process. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. Microscopic particles present in the manufacturing environment and slight variations in the parameters of manufacturing steps can all lead to the geometrical and electrical properties of an IC to deviate from those generated at the end of the design process. Those defects can cause various types of malfunctioning, depending on the IC topology and the nature of the defect. To relive the burden placed on IC design and manufacturing originated with ever-increasing costs associated with testing and debugging of complex mixed-signal electronic systems, several circuit techniques and algorithms are developed and incorporated in proposed ATPG, DfT and BIST methodologies. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. With the use of dedicated sensors, which exploit knowledge of the circuit structure and the specific defect mechanisms, the method described in this thesis facilitates early and fast identification of excessive process parameter variation effects. The expectation-maximization algorithm makes the estimation problem more tractable and also yields good estimates of the parameters for small sample sizes. To allow the test guidance with the information obtained through monitoring process variations implemented adjusted support vector machine classifier simultaneously minimize the empirical classification error and maximize the geometric margin. On a positive note, the use of digital enhancing calibration techniques reduces the need for expensive technologies with special fabrication steps. Indeed, the extra cost of digital processing is normally affordable as the use of submicron mixed signal technologies allows for efficient usage of silicon area even for relatively complex algorithms. Employed adaptive filtering algorithm for error estimation offers the small number of operations per iteration and does not require correlation function calculation nor matrix inversions. The presented foreground calibration algorithm does not need any dedicated test signal and does not require a part of the conversion time. It works continuously and with every signal applied to the A/D converter. The feasibility of the method for on-line and off-line debugging and calibration has been verified by experimental measurements from the silicon prototype fabricated in standard single poly, six metal 0.09-µm CMOS process

Advanced Digital Signal Processing Techniques for High-Speed Optical Links

L'abstract è presente nell'allegato / the abstract is in the attachmen

Novel real - time system design for floating - point sub - Nyquist Multi - coset signal blind reconstruction

We propose a novel real-time system design for multiband signal blind reconstruction using multi-coset sampling theory. Multi-channel signals are acquired under sub-Nyquist sampling frequency to perfectly reconstruct the original signal spectrum. A novel system design with Field-Programmable Gate Array (FPGA) implementation is presented in this report. There are two main contributions introduced by this design. Firstly, the FPGA system uses 32-bit single precision floating point dataflow rather than conventional 16-bit fixed point to recover signals with much lower Signal-Noise Ratio (SNR). Secondly, we introduce a novel Jacobi CORDIC eigenvalue decomposition (EVD) core using parallel pivot-seeking circuit and parallel 3-CORDIC design to improve speed significantly. Hermitian matrices of dimensions from 2 to 10 are tested to compare conventional 2-CORDIC EVD and the proposed EVD. The proposed EVD effectively reduces on average 36% of processing time for mesh connection system and over 50% for parallel system. Part of this final year project was written as a conference paper accepted by the 2015 Annual International Symposium of Circuits and Systems (ISCAS 2015) for lecture presentation on May 25, 2015. The conference is to be held at the Cultural Centre of Belem, Lisbon, Portugal from May 24 – 28, 2015.Bachelor of Engineerin