3 research outputs found
Power supply noise in delay testing
As technology scales into the Deep Sub-Micron (DSM) regime, circuit designs have
become more and more sensitive to power supply noise. Excessive noise can significantly
affect the timing performance of DSM designs and cause non-trivial additional delay. In
delay test generation, test compaction and test fill techniques can produce excessive power
supply noise. This will eventually result in delay test overkill.
To reduce this overkill, we propose a low-cost pattern-dependent approach to analyze
noise-induced delay variation for each delay test pattern applied to the design. Two noise
models have been proposed to address array bond and wire bond power supply networks,
and they are experimentally validated and compared. Delay model is then applied to
calculate path delay under noise. This analysis approach can be integrated into static test
compaction or test fill tools to control supply noise level of delay tests. We also propose
an algorithm to predict transition count of a circuit, which can be applied to control
switching activity during dynamic compaction.
Experiments have been performed on ISCAS89 benchmark circuits. Results show that
compacted delay test patterns generated by our compaction tool can meet a moderate
noise or delay constraint with only a small increase in compacted test set size. Take the benchmark circuit s38417 for example: a 10% delay increase constraint only results in
1.6% increase in compacted test set size in our experiments. In addition, different test fill
techniques have a significant impact on path delay. In our work, a test fill tool with supply
noise analysis has been developed to compare several test fill techniques, and results show
that the test fill strategy significant affect switching activity, power supply noise and
delay. For instance, patterns with minimum transition fill produce less noise-induced
delay than random fill. Silicon results also show that test patterns filled in different ways
can cause as much as 14% delay variation on target paths. In conclusion, we must take
noise into consideration when delay test patterns are generated
Noise propagation and failure criteria for vlsi designs
Noise analysis has become a critical concern in advanced chip designs. Traditional methods suffer from two common issues. First, noise that is propagated through the driver of a net is combined with noise injected by capacitively coupled aggressor nets using linear summation. Since this ignores the non-linear behavior of the driver gate the noise that develops on a net can be significantly underestimated. We therefore propose a new linear model that accurately combines propagated and injected noise on a net and which maintains the efficiency of linear simulation. After the propagated and injected noise are correctly combined on a victim net, it is necessary to determine if the noise can result in a functional failure. This is the second issue that we discuss in this paper. Traditionally, noise failure criteria have been based on unity gain points of the DC or AC transfer curves. However, we will show that for digital designs, these approaches can result in a pessimistic analysis in some cases, while in other cases, they allow circuit operation that is extremely close to regions that are unstable and do not allow sufficient margin for error in the analysis. In this paper, we compare the effectiveness of the discussed noise failure criteria and also present a propagation based method, which is intended to overcome these drawbacks. The proposed methods were implemented in a noise analysis tool and we demonstrate results on industrial circuits