Conversor CC-CC elevador de tensão para aplicações de energy harvesting

Ao longo das últimas décadas os dispositivos portáteis alimentados com baixa tensão têm vindo a aumentar e, consequentemente, algumas fontes de recolha de energia a partir do ambiente envolvente. Para permitir a aplicação dessas fontes de recolha de energia a dispositivos eletrónicos portáteis, verificou-se a necessidade do uso de conversores Corrente Contínua-Corrente Contínua (CC-CC) eficientes. Neste sentido, surge o tema para esta dissertação, na qual se pretende desenvolver um conversor CC-CC elevador de tensão, dedicado a aplicações de recolha de energia. Este conversor deverá ser integrado em tecnologia Complementary Metal-Oxide-Semiconductor (CMOS) de 130nm para operar em alta frequência (na ordem dos MHz), tendo como objetivo converter tensões da ordem dos 500mV em 2,4V. O projeto é assistido em ambiente Electronic Design Automation (EDA), recorrendo à ferramenta Cadence Design Environment (CDE) e ao respetivo kit da tecnologia CMOS, sendo validado com simulações em situações extremas, conhecidas como simulação de corners. O circuito é projetado e testado em esquema elétrico, permitindo obter 2,4V com tensões de entrada a partir de 0,4V até 0,6V. Para elaborar a planta em simulador otimiza-se o circuito para a tensão de entrada a 0,5V. A partir da planta é feita a extração do circuito, incluindo assim todos os parâmetros parasitas do processo. Finalmente, o conversor projetado é baseado numa arquitetura híbrida, indutiva e capacitiva, permitindo converter uma tensão de 0,5V para 2,4V, com uma carga de 10KΩ e frequência de 10 MHz, sendo que a área de implementação da planta do circuito é de 303,974mm2.In the last few decades, the number of low-voltage portable devices have been increasing and, with them, some energy harvesting sources from the environment. To allow the application of these energy sources to electronic portable devices, the need of Direct Current-Direct Current (DC-DC) converters was perceived. Therefore the topic for this dissertation presents itself, in which is intended the development of a DC-DC boost converter, dedicated to energy harvesting applications. This converter should be integrated in a Complementary Metal-Oxide-Semiconductor (CMOS) technology, to operate in high frequency (MHz), and its goal being to convert voltages from 500mV to 2.4V. The project is assisted in Electronic Design Automation environment (EDA), resorting to the Cadence Design Environment tool (CDE) and the respective CMOS technology kit. This is validated by extreme situation simulations, known as corners’ simulation. The circuit is designed and tested in schematic, allowing to get 2.4V with an entrance voltage from 0.4V to 0.6V. To make the layout in the simulator, the circuit is optimized to an entrance voltage of 0.5V. From the layout it’s made a circuit extraction, including all the process parasite parameters. Ultimately, the projected converter is based on a hybrid architecture, inductive and capacitive, allowing to convert a voltage of 0.5V to 2.4V, with a charge of 10 KΩ and a frequency of 10 MHz, being the implementation area of the circuit layout 303,974mm2

Génération de stimuli efficaces en énergie pour la microstimulation électrique intracorticale

RÉSUMÉ Ce mémoire a comme objectif principal la mise en oeuvre de circuits dédiés à l’amélioration de l’efficacité de la stimulation électrique de tissus situés au niveau du cortex visuel primaire. Le stimulateur proposé permet la génération de nouveaux stimuli flexibles de forme exponentielle et demi-sinusoïdale dans l’optique de réduire la consommation de puissance globale de l’implant. En plus d’être potentiellement plus efficaces que les stimulations rectangulaires standard pour exciter les tissus, ces formes d’impulsions permettraient également de réduire la concentration d’ions toxiques relâchés par les électrodes. Le second objectif de ce projet est de permettre la stimulation à pleine échelle, soit au moins 150 µA, à travers l’interface microélectrode-tissus qui est caractérisée par une impédance élevée. Un étage de sortie à haute-tension a donc également été réalisé afin de générer des tensions d’alimentation d’environ ±9 V et d’augmenter ainsi l’excursion de tension des stimuli tout en étant entièrement intégré. Une architecture comportant deux circuits intégrés indépendants est proposée dans ce mémoire. Le générateur de stimuli est implémenté dans la technologie CMOS 0,18-µ m 1,8V/3,3V de TSMC afin de limiter sa consommation de puissance. Pour ce qui est de l’étage de sortie, il est intégré à l’aide du procédé C08E CMOS/DMOS 0,8-µ m 5V/20V de DALSA Semiconductors, technologie supportant les niveaux de tension requis.Les deux puces ainsi fabriquées ont été testées. L’intensité des stimuli rectangulaires couvre une plage de 1,6 à 167,2 µ A des erreurs de non-linéarité différentielle et intégrale de 0,10 et 0,16 LSB respectivement. Les impulsions exponentielles ont une plage dynamique de 34,36 dB pour une erreur de ±0,5 dB par rapport à la fonction théorique. La consommation de puissance du générateur de stimuli atteint en moyenne 29,1 µW en mode rectangulaire et de 28,5 à 88,3 µ W en mode exponentiel. Les résultats obtenus pour la demi-sinusoïde proviennent de simulations. En moyenne, 80,2 % de la durée des impulsions demi-sinusoïdales a une erreur inférieure à ±1 % par rapport à la fonction idéale. Le générateur de stimuli complet consomme de 46,7 à 199,1 µW en mode demi-sinusoïdal. En ce qui a trait à l’étage de sortie, des tensions de 8,95 et -8,46 V sont générées avec succès, permettant à l’excursion de tension d’atteindre 13,6 V à travers une charge de 100 kΩ.----------ABSTRACT This master thesis’ main objective is the implementation of circuits dedicated to electrical stimulation efficiency enhancement for tissues in the primary visual cortex. The proposed stimulator allows novel stimuli waveform generation such as flexible exponential and half-sine pulses in order to reduce the implant’s global power consumption. In addition of being potentially more efficient to excite neural tissues than standard rectangular pulse-based stimulations, these waveforms should also reduce toxic ions concentration released by the electrodes. Moreover, this project’s second objective is to allow full-scale stimulation, i.e., at least 150 µA, through high-impedance microelectrode-tissue interfaces. A high-voltage output stage has also been realized to generate ±9 V voltage supplies to increase the voltage swing while being fully-integrated. An architecture composed of two independent integrated circuits has been proposed. The stimuli generator is implemented in TSMC CMOS 0.18-µ m 1.8V/3.3V technology to limit its power consumption. On the other hand, the output stage is integrated in C08E CMOS/DMOS 0.8- µm 5V/20V process from DALSA Semiconductors as this technology supports the required voltage levels.These two fabricated chips were tested. Rectangular stimuli intensity varies from 1.6 to 167.2 µA with differential and integral nonlinearities of 0.10 and 0.16 LSB, respectively. Exponential pulses show a dynamic range of 34.36 dB for an error of ±0.5 dB with the theoretical waveform. The stimuli generator’s power consumption reaches an average of 29.1 µW in rectangular mode and from 28.5 to 88.3 µW in exponential mode. Half-sine results are obtained from simulations. An average of 80.2 % of half-sine pulse duration has an error lower than ±1 % with the ideal sine function. The whole stimuli generator consumes from 46.7 to 199.1 µW in half-sine mode. For the output stage, voltages of 8.95 and -8.46 V are successfully generated, allowing the output voltage compliance to reach 13.6 V through a 100 kΩ load. However, this chip dissipates 51.37 mW when operating normally

Charge Pumps for Implantable Microstimulators in Low and High-Voltage Technologies

RÉSUMÉ L'objectif principal de cette thèse est de concevoir et mettre en œuvre une pompe de charge qui peut produire suffisamment de tension afin de l’implémenter à un système de prothèse visuelle, conçue par le laboratoire PolyStim neurotechnologies. Il a été constaté que l'une des parties les plus consommatrices d'énergie de l'ensemble du système de prothèse visuelle est la pompe de charge. En raison de la nature variable du tissu nerveux et de l'interface d’électrode, la tension nécessaire par stimuler le tissu nerveux est très élevé et consomme extrêmement d’énergie. En outre, afin de fournir du courant biphasique aux électrodes il faut produire des tensions positives et négatives. La génération de tension négative est très difficile, surtout dans les technologies à faible tension compte tenu des limites de la technologie. Le premier objectif du projet est de générer la haute tension nécessaire qui va consommer une faible puissance statique. La technologie de haute tension a été utilisée dans le but d’atteindre cet objectif. Le deuxième objectif est de générer la tension requise dans la technologie de basse tension et ainsi surmonter les limites de la technologie. Dans les deux cas, une attention particulière a été portée afin que personne ne latch-up apparaît pour le cycle négatif. L'architecture de la conception proposée a été présentée dans cette thèse. La pompe de charge a été conçu et mis en oeuvre à la fois dans la technologie CMOS 0,8 μm offert par TELEDYNE DALSA et technologie 0,13 μm CMOS offert par IBM. En raison de la tension requise, 0,8 μm technologie a été utilisée pour atteindre la sortie et conçu pour minimiser la consommation de puissance statique. La même architecture a été mise en oeuvre en technologie 0,13 μm pour enquêter sur la tension de sortie obtenue avec une faible consommation électrique. Les deux puces ont été testées en laboratoire PolyStim. Les résultats testés ont montré une variation moyenne très faible de déviation inférieure à 5% par rapport au résultat de simulation. Pour la conception en 0,8 µm, nous avons été en mesure d'obtenir plus de 25 V avec une consommation électrique très faible d’énergie statique de 3,846 mW et une charge d'entraînement maximum de 2 mA avec un maximum d'efficacité de 84,2%. Pour le même processus en 0,13 µm, les resultats ont été plus que 20V, 0,913 mW, 500 µA, et 85,2% respectivement.----------ABSTRACT The main objective of the thesis is to design and implement a charge pump that can produce enough voltage required to be implemented to the visual prosthesis system, designed by the PolyStim Neurotechnologies laboratory. It has been found that one of the most power consuming parts of the whole visual prosthesis system is the charge pump. Due to the variable nature of the nerve tissue and electrode interface, the required voltage of stimulating the nerve tissue is very high and thus extremely power consuming. Also, in order to provide biphasic current to the electrodes, there is a requirement of generating both positive and negative voltages. Generating negative voltage is very hard especially in low voltage technologies considering the technology limitations. The first objective of the project is to generate required high voltage that will consume low static power. High voltage technology has been used to achieve the goal. The second objective is to generate the required voltage in low voltage technology overcoming the technology limitations. In both cases, special care has been taken so that no latch-up occurs for the negative cycle. Architecture of the proposed design has been presented in this thesis. The charge pump has been designed and implemented in both 0.8 µm CMOS technology offered by TELEDYNE DALSA and 0.13 µm CMOS technology offered by IBM. Because of the required voltage, 0.8 µm technology has been used to achieve the output and designed to minimize the static power consumption. The same architecture has been implemented in 0.13 µm technology to investigate the achievable output voltage with low power consumption. Both the chips have been tested in polyStim laboratory. The tested results have shown very low variation of less than 5% average deflection from the simulation output. For the design in 0.8 µm, we have been able to get more than 25 V output with very low static power consumption of 3.846 mW and maximum drive load of 2 mA with maximum efficiency of 84.2%. For the same design in 0.13 µm, the outputs were more than 20V, 0.913 mW, 500 µA, and 85.2% respectively

Custom Silicon for Low-Cost Information Dissemination among Illiterate People Groups.

In this work, we present an Information and Communications Technology (ICT) device that improves the quality of life of the poorest people in the world by enabling information access through Very Large Scale Integrated chips. Identified as agrarian farmers that subsist on less than $2 a day, the world’s poorest people face many challenges that make developing an ICT device difficult. We argue that prior devices do not adequately overcome the unique problems of: cost, power, connectivity, usability, robustness, and illiteracy. We show that while many of these constraints need to be addressed, cost represents the greatest fundamental challenge to widespread use and adoption of ICT devices. To address this challenge, this thesis presents a custom silicon chip design referred to as “Literacy in Technology” (LIT). LIT enables an audio computer ICT device to overcome the constraints through a number of techniques: A high level of integration of the components on a single die reduces its cost and form-factor. LIT’s power management system ensures long lifetime through energy consumption reduction by exploiting unique characteristics of Carbon-Zinc batteries, common in the developing world. Its Hybrid Switch Capacitor Network addresses off-chip component cost by using only inexpensive capacitors, further reducing cost. LIT’s unique memory hierarchy, a large on-chip cache backed directly by NAND Flash combined with a simple and low area core, reduces cost by not requiring DRAM or NOR Flash. LIT’s power-on-reset and brown-out-detection overcomes Carbon-Zinc battery’s high hysteresis resulting in higher robustness. LIT further reduces cost through overloading the functionality of PCB traces as both a human input interface and as information transfer from device to device. We show how LIT and its unique solutions allow us to develop an ICT device targeted towards developing regions at a total estimated electronics cost of less than$6. Furthermore, LIT reduces recurring costs through lowered energy consumption and increased robustness when compared to previous ICT devices. Although many of our novel technical contributions were motivated by strong price elasticity in developing regions, the techniques developed are equally applicable to rugged, low-power systems targeted at mainstream applications.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/102429/1/zhiyoong_1.pd

Design of new four-phase clock scheme & generation circuits for low-voltage charge pumps

眾所週知磊浦電路在快閃式或者電子可擦拭記憶體上扮演非常重要的角色。例如，在寫入或抹除時，需要非常高的正電壓或負電壓。除此之外，它們也經常的被廣泛應用在切換電容式系統(如類比數位轉換器，或濾波器)上。最近，隨著可攜式通訊系統的普遍發展，低電壓及低消耗功率的電路系統已成為設計的趨勢。因此，針對低電壓四相位磊浦電路，一種使用高電壓時脈產生器來產生倍壓時脈的新時脈模式，及新式四相位產生電路將在本萹論文中提出。兩種主要的因素導致於磊浦電路的輸出電壓與效能的降低，即為場效電晶體的高臨界電壓和本體基板效應。因此，提出一種新的技術來降低上述因素的影響，即提供連接主要電晶體閘極的電容一倍壓時脈的技術，以提高磊浦電路的電壓增益。使用此一新技術，可使磊浦電路在低電壓時也能獲得較高的負電壓及正電壓增益。此外，針對低電壓四相位磊浦電路，一種實用的新四相位產生電路可以一組時脈簡易的實現。It is well known that the charge pumping circuits play a very important role in Flash memory or EEPROM circuits. For example, programming or erasing the Flash memory cells needs very high positive and negative voltages. Those are also widely used in switch capacitor systems, such as A/D, D/A, and filter systems. The recent development of portable communication systems has driven to the trend to low-voltage and low-power circuits. Therefore, this thesis proposed the new efficient clock scheme for low-voltage four-phase charge pumping circuits utilizing high voltage clock generator to generate boosted clocks and new four-phase generation circuits for low-voltage charge pumps. The two major factors limiting the pumping gain and efficiency are the body effect and the threshold voltage. One technique was proposed to minimize the influence of them. That is the boosted clocks are applied on the capacitors connected to the gates of the major pumping transistors to enhance the pumping gain. With the new technique, the four-phase charge pumping circuits have high positive or negative boosted voltages at very low supply voltages. In addition, a new four-phase generator for the four-phase charge pumping circuits for very low supply voltage can be practical and easily implemented using single clock.Abstract (in Chinese)……………………………………………i Abstract (in English)……………………………………………ii Acknowledgements……………………………………………………iv Contents………………………………………………………………v List of Figures………………………………………………………x Chapter 1………………………………………………………1 Introduction…………………………………………………………1 1.1Application of charge pumping circuits……………………1 1.1.1Memory circuits…………………………………………………2 1.1.2Switch capacitor system………………………………………6 1.2Low-voltage / Low-power design…………………………………9 1.2.1The reasons…………………………………………………………9 1.2.2The trends…………………………………………………………12 1.3Thesis organization………………………………………………16 Chapter 2………………………………………………………18 Existing Charge pump circuits……………………………………18 2.1Dickson charge pump circuit……………………………………18 2.1.1Operation principles……………………………………………20 2.1.2Limitations……………………………………………………23 2.2Other charge pump circuits……………………………………24 2.2.1Overviews of different charge pumping circuits…………………..24 2.2.2Limitations……………………………………………………30 2.3Ncp-x charge pumping circuits………………………………31 2.3.1Ncp-1 charge pump……………………………………………31 2.3.2Ncp-2 charge pump……………………………………………33 2.3.3Ncp-3 charge pump……………………………………………34 2.3.4The advantages and drawbacks………………………………36 2.4New-x charge pumping circuits………………………………37 2.4.1New-1 charge pump ………………………………………37 2.4.2New-2 charge pump ……………………………………………40 2.4.3The advantages and drawbacks………………………………40 2.5Summary………………………………………………………………42 Chapter 3…………………………………………………………43 New 4-phase clock scheme and generator .………………………43 3.1The idea of design………………………………………………43 3.1.1the structures…………………………………………………43 3.1.2the principle..………………………………………………47 3.2New 4-phase charge pumps………………………………………48 3.2.1H_MOS charge pumping circuit………………………………48 3.2.2H_R charge pumping circuit …………………………………51 3.3New four-phase clock generation circuit……………………53 3.4Summary………………………………………………………………56 Chapter 4…………………………………………………………57 Results of Simulation and Implementation………………………57 4.1Simulation conditions……………………………………………57 4.2Simulation results ………………………………………………58 4.3Chip implementation………………………………………………65 4.3.1Physical Layout for H_MOS circuit…………………………65 4.3.2Measurement Result for H_MOS circuit………………………68 4.4 Summary………………………………………………………69 Chapter 5…………………………………………………………….70 Conclusions…………………………………………………………………70 5.1Reviews…………………………………………………………70 5.1Conclusions………………………………………………72 5.2 Future works…………………………………………………………73 Bibliography……………………………………………………………74 Chapter 1:………………………………………74 Chapter 2:………………………………………76 Chapter 3:………………………………………77 Chapter 4:………………………………………77 Chapter 5:………………………………………7