14,545 research outputs found
The Project Scheduling Problem with Non-Deterministic Activities Duration: A Literature Review
Purpose: The goal of this article is to provide an extensive literature review of the models and solution procedures proposed by many researchers interested on the Project Scheduling Problem with nondeterministic activities duration. Design/methodology/approach: This paper presents an exhaustive literature review, identifying the existing models where the activities duration were taken as uncertain or random parameters. In order to get published articles since 1996, was employed the Scopus database. The articles were selected on the basis of reviews of abstracts, methodologies, and conclusions. The results were classified according to following characteristics: year of publication, mathematical representation of the activities duration, solution techniques applied, and type of problem solved. Findings: Genetic Algorithms (GA) was pointed out as the main solution technique employed by researchers, and the Resource-Constrained Project Scheduling Problem (RCPSP) as the most studied type of problem. On the other hand, the application of new solution techniques, and the possibility of incorporating traditional methods into new PSP variants was presented as research trends. Originality/value: This literature review contents not only a descriptive analysis of the published articles but also a statistical information section in order to examine the state of the research activity carried out in relation to the Project Scheduling Problem with non-deterministic activities duration.Peer Reviewe
Optimizing Scrubbing by Netlist Analysis for FPGA Configuration Bit Classification and Floorplanning
Existing scrubbing techniques for SEU mitigation on FPGAs do not guarantee an
error-free operation after SEU recovering if the affected configuration bits do
belong to feedback loops of the implemented circuits. In this paper, we a)
provide a netlist-based circuit analysis technique to distinguish so-called
critical configuration bits from essential bits in order to identify
configuration bits which will need also state-restoring actions after a
recovered SEU and which not. Furthermore, b) an alternative classification
approach using fault injection is developed in order to compare both
classification techniques. Moreover, c) we will propose a floorplanning
approach for reducing the effective number of scrubbed frames and d),
experimental results will give evidence that our optimization methodology not
only allows to detect errors earlier but also to minimize the
Mean-Time-To-Repair (MTTR) of a circuit considerably. In particular, we show
that by using our approach, the MTTR for datapath-intensive circuits can be
reduced by up to 48.5% in comparison to standard approaches
EffiTest: Efficient Delay Test and Statistical Prediction for Configuring Post-silicon Tunable Buffers
At nanometer manufacturing technology nodes, process variations significantly
affect circuit performance. To combat them, post- silicon clock tuning buffers
can be deployed to balance timing bud- gets of critical paths for each
individual chip after manufacturing. The challenge of this method is that path
delays should be mea- sured for each chip to configure the tuning buffers
properly. Current methods for this delay measurement rely on path-wise
frequency stepping. This strategy, however, requires too much time from ex-
pensive testers. In this paper, we propose an efficient delay test framework
(EffiTest) to solve the post-silicon testing problem by aligning path delays
using the already-existing tuning buffers in the circuit. In addition, we only
test representative paths and the delays of other paths are estimated by
statistical delay prediction. Exper- imental results demonstrate that the
proposed method can reduce the number of frequency stepping iterations by more
than 94% with only a slight yield loss.Comment: ACM/IEEE Design Automation Conference (DAC), June 201
FPSA: A Full System Stack Solution for Reconfigurable ReRAM-based NN Accelerator Architecture
Neural Network (NN) accelerators with emerging ReRAM (resistive random access
memory) technologies have been investigated as one of the promising solutions
to address the \textit{memory wall} challenge, due to the unique capability of
\textit{processing-in-memory} within ReRAM-crossbar-based processing elements
(PEs). However, the high efficiency and high density advantages of ReRAM have
not been fully utilized due to the huge communication demands among PEs and the
overhead of peripheral circuits.
In this paper, we propose a full system stack solution, composed of a
reconfigurable architecture design, Field Programmable Synapse Array (FPSA) and
its software system including neural synthesizer, temporal-to-spatial mapper,
and placement & routing. We highly leverage the software system to make the
hardware design compact and efficient. To satisfy the high-performance
communication demand, we optimize it with a reconfigurable routing architecture
and the placement & routing tool. To improve the computational density, we
greatly simplify the PE circuit with the spiking schema and then adopt neural
synthesizer to enable the high density computation-resources to support
different kinds of NN operations. In addition, we provide spiking memory blocks
(SMBs) and configurable logic blocks (CLBs) in hardware and leverage the
temporal-to-spatial mapper to utilize them to balance the storage and
computation requirements of NN. Owing to the end-to-end software system, we can
efficiently deploy existing deep neural networks to FPSA. Evaluations show
that, compared to one of state-of-the-art ReRAM-based NN accelerators, PRIME,
the computational density of FPSA improves by 31x; for representative NNs, its
inference performance can achieve up to 1000x speedup.Comment: Accepted by ASPLOS 201
Re-designing Dynamic Content Delivery in the Light of a Virtualized Infrastructure
We explore the opportunities and design options enabled by novel SDN and NFV
technologies, by re-designing a dynamic Content Delivery Network (CDN) service.
Our system, named MOSTO, provides performance levels comparable to that of a
regular CDN, but does not require the deployment of a large distributed
infrastructure. In the process of designing the system, we identify relevant
functions that could be integrated in the future Internet infrastructure. Such
functions greatly simplify the design and effectiveness of services such as
MOSTO. We demonstrate our system using a mixture of simulation, emulation,
testbed experiments and by realizing a proof-of-concept deployment in a
planet-wide commercial cloud system.Comment: Extended version of the paper accepted for publication in JSAC
special issue on Emerging Technologies in Software-Driven Communication -
November 201
Runtime Scheduling, Allocation, and Execution of Real-Time Hardware Tasks onto Xilinx FPGAs Subject to Fault Occurrence
This paper describes a novel way to exploit the computation capabilities delivered by modern Field-Programmable Gate Arrays (FPGAs), not only towards a higher performance, but also towards an improved reliability. Computation-specific pieces of circuitry are dynamically scheduled and allocated to different resources on the chip based on a set of novel algorithms which are described in detail in this article. These algorithms consider most of the technological constraints existing in modern partially reconfigurable FPGAs as well as spontaneously occurring faults and emerging permanent damage in the silicon substrate of the chip. In addition, the algorithms target other important aspects such as communications and synchronization among the different computations that are carried out, either concurrently or at different times. The effectiveness of the proposed algorithms is tested by means of a wide range of synthetic simulations, and, notably, a proof-of-concept implementation of them using real FPGA hardware is outlined
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