Ternary jitter-based true random number generator

© Published under licence by IOP Publishing Ltd.In this paper a novel family of generators producing true uniform random numbers in ternary logic is presented. The generator consists of a number of identical ternary logic combinational units connected into a ring. All the units are provided to have a random delay time, and this time is supposed to be distributed in accordance with an exponential distribution. All delays are supposed to be independent events. The theory of the generator is based on Erlang equations. The generator can be used for test production in various systems. Features of multidimensional random vectors, produced by the generator, are discussed

Ternary jitter-based true random number generator

© Published under licence by IOP Publishing Ltd.In this paper a novel family of generators producing true uniform random numbers in ternary logic is presented. The generator consists of a number of identical ternary logic combinational units connected into a ring. All the units are provided to have a random delay time, and this time is supposed to be distributed in accordance with an exponential distribution. All delays are supposed to be independent events. The theory of the generator is based on Erlang equations. The generator can be used for test production in various systems. Features of multidimensional random vectors, produced by the generator, are discussed

A Random Number Generator Using Ring Oscillators and SHA-256 as Post-Processing

Today, cryptographic security depends primarily on having strong keys and keeping them secret. The keys should be produced by a reliable and robust to external manipulations generators of random numbers. To hamper different attacks, the generators should be implemented in the same chip as a cryptographic system using random numbers. It forces a designer to create a random number generator purely digitally. Unfortunately, the obtained sequences are biased and do not pass many statistical tests. Therefore an output of the random number generator has to be subjected to a transformation called post-processing. In this paper the hash function SHA-256 as post-processing of bits produced by a combined random bit generator using jitter observed in ring oscillators (ROs) is proposed. All components – the random number generator and the SHA-256, are implemented in a single Field Programmable Gate Array (FPGA). We expect that the proposed solution, implemented in the same FPGA together with a cryptographic system, is more attack-resistant owing to many sources of randomness with significantly different nominal frequencies

Complex Dynamics in Digital Nonlinear Oscillators: Experimental Analysis and Verification

A specific topology of Digital Nonlinear Oscillators (DNOs) has been implemented by using commercial off-the-shelf digital components to experimentally verify and demonstrate the capability of these circuits to support complex dynamics, independently from their implementation technology. In detail, a direct experimental evidence of the DNO dynamical behavior is presented at the analog level with a bifurcation diagram analysis, investigation of periodic and chaotic attractors, and dynamical stability. The autonomous circuit has been investigated as a source of entropy, adopting different figures of merit, including the Lempel–Ziv Complexity, to evaluate the dynamics measured under different operating conditions

Proposal and Analysis of a Novel Class of PUFs Based on Galois Ring Oscillators

In this article, the possibility of using Galois ring oscillators to construct physically unclonable functions (PUFs) has been studied. The idea is to use novel PUF architectures, similar as the ring oscillator PUFs that, instead of comparing frequencies, compare the statistical bias of pairs of oscillators implemented in different locations. To study the viability of these systems, three different Galois oscillators have been implemented in several locations in several FPGAs and we have studied the main properties of their bias: repeatability, variability with the location, variability with the FPGA and spatial autocorrelation. Based on this study, we have determined that the bias of these oscillators meet the requirements that are needed to be used to construct a PUF. Finally, a PUF based on comparing the bias of neighboring 7-LUT Galois ring oscillators have been implemented and analyzed. The experimental results show that this PUF generates uniform responses that are highly reproducible and unique, making this PUF suitable for being used in identification applications

Producing Random Bits with Delay-Line Based Ring Oscillators

One of the sources of randomness for a random bit generator (RBG) is jitter present in rectangular signals produced by ring oscillators (ROs). This paper presents a novel approach for the design of delays used in these oscillators. We suggest using delay elements made on carry4 primitives instead of series of inverters or latches considered in the literature. It enables the construction of many high frequency ring oscillators with different nominal frequencies in the same field programmable gate array (FPGA). To assess the unpredictability of bits produced by RO-based RBG, the restarts mechanism, proposed in earlier papers, was used. The output sequences pass all NIST 800-22 statistical tests for smaller number of ring oscillators than the constructions described in the literature. Due to the number of ROs with different nominal frequencies and the method of construction of carry4 primitives, it is expected that the proposed RBG is more robust to cryptographic attacks than RBGs using inverters or latches as delay element

Fibonacci Ring Oscillators as True Random Number Generators - A Security Risk

Fibonacci ring oscillators are shown to have a risk to oscillate periodically instead of chaotically. The security implications of this are discussed. The probability of the occurrence of the periodic oscillations is determined experimentally on an FPGA for Fibonacci ring oscillators of lengths 16 and 32. Means to overcome the problem of the periodic oscillations are also discussed

Random Number Generation Based on Oscillatory Metastability in Ring Circuits

Random number generator designs are discussed, which utilize oscillatory metastability, induced by switching between two stable states of ring-connected digital gates. For a short time after the switch-over the circuits behave quite randomly, influenced by the circuit noise. We provide simple programs, which simulate the fundamental behavior of our circuits. We also present a mathematical model and theoretical explanations of the underlying physical phenomena, the random phase drift and pulse decay. These also illuminate the principles of other recently published random number generators. The feasibility of the designs was confirmed by FPGA prototypes. These random number generators are small, fast and built of standard logic gates. The simplest example contains just one XOR gate as the source of randomness

Compact Ring-LWE Cryptoprocessor

Abstract. In this paper we propose an efficient and compact processor for a ring-LWE based encryption scheme. We present three optimizations for the Num-ber Theoretic Transform (NTT) used for polynomial multiplication: we avoid pre-processing in the negative wrapped convolution by merging it with the main algo-rithm, we reduce the fixed computation cost of the twiddle factors and propose an advanced memory access scheme. These optimization techniques reduce both the cycle and memory requirements. Finally, we also propose an optimization of the ring-LWE encryption system that reduces the number of NTT operations from five to four resulting in a 20 % speed-up. We use these computational optimiza-tions along with several architectural optimizations to design an instruction-set ring-LWE cryptoprocessor. For dimension 256, our processor performs encryp-tion/decryption operations in 20/9 µs on a Virtex 6 FPGA and only requires 1349 LUTs, 860 FFs, 1 DSP-MULT and 2 BRAMs. Similarly for dimension 512, the processor takes 48/21 µs for performing encryption/decryption operations and only requires 1536 LUTs, 953 FFs, 1 DSP-MULT and 3 BRAMs. Our pro-cessors are therefore more than three times smaller than the current state of the art hardware implementations, whilst running somewhat faster

Generador hardware de claves basado en funciones físicamente no clonables

En este Trabajo Fin de Grado se ha llevado a cabo el estudio de las funciones físicamente no clonables (PUFs), profundizando en un caso concreto: las funciones físicamente no clonables basadas en osciladores de anillo de Galois, un tipo de oscilador de anillo diferente al oscilador de anillo simple.Se ha realizado tanto un análisis teórico como un estudio experimental de dichos sistemas.En la parte teórica se ha llevado a cabo un estudio de las PUFs, así como del mencionado oscilador de anillo de Galois. Además de esto, se ha estudiado también el flujo de diseño y la sintaxis necesaria para implementar físicamente las PUF en una matriz de puertas lógicas programable (FPGA), empleando lenguajes de descripción hardware tales como VHDL y verilog en el software Vivado.Por otro lado, la parte experimental ha consistido en la toma de medidas en el laboratorio con las PUF ya implementadas en la FPGA, y el posterior tratamiento de datos y análisis de los resultados obtenidos.<br /