New Algorithms for Minimizing the Longest Wire Length During Circuit Compaction

Consider the problem of performing 1-dimensional circuit compaction for a layout containing n h horizontal wires and n layout cells. We present new and efficient constraint-graph based algorithms for generating a compacted layout in which either the length of the longest wires or a user-specified tradeoff function between the layout width and the longest wire length is minimized. Both algorithms have an O(n h \Delta n log n) running time. The concept employed by our algorithms is that of assigning speeds to the layout cells. Speeds are computed by performing path computations in subgraphs of the constraint graphs. A compacted layout is generated over a number of iterations, with each iteration first determining speeds and then moving the layout elements to the right according to the computed speeds. Each iteration produces a better layout and after at most n \Delta n h iterartions the final layout is produced. Keywords: Analysis of algorithms, circuit layout, compaction, layout width..