3 research outputs found
Memristor-based design solutions for mitigating parametric variations in IoT applications
PhD ThesisRapid advancement of the internet of things (IoT) is predicated by two important factors
of the electronic technology, namely device size and energy-efficiency. With smaller
size comes the problem of process, voltage and temperature (PVT) variations of delays
which are the key operational parameters of devices. Parametric variability is also
an obstacle on the way to allowing devices to work in systems with unpredictable
power sources, such as those powered by energy-harvesters. Designers tackle these
problems holistically by developing new techniques such as asynchronous logic, where
mechanisms such as matching delays are widely used to adapt to delay variations. To
mitigate energy efficiency and power interruption issues the matching delays need to
be ideally retained in a non-volatile storage. Meanwhile, a resistive memory called
memristor becomes a promising component for power-restricted applications owing to
its inherent non-volatility. While providing non-volatility, the use of memristor in delay
matching incurs some power overheads. This creates the first challenge on the way of
introducing memristors into IoT devices for the delay matching.
Another important factor affecting the use of memristors in IoT devices is the
dependence of the memristor value on temperature. For example, a memristance
decoder used in the memristor-based components must be able to correct the read data
without incurring significant overheads on the overall system. This creates the second
challenge for overcoming the temperature effect in memristance decoding process.
In this research, we propose methods for improving PVT tolerance and energy
characteristics of IoT devices from the perspective of above two main challenges:
(i) utilising memristor to enhance the energy efficiency of the delay element (DE), and
(ii) improving the temperature awareness and energy robustness of the memristance
decoder.
For memristor-based delay element (MemDE), we applied a memristor between two
inverters to vary the path resistance, which determines the RC delay. This allows power
saving due to the low number of switching components and the absence of external delay
storage. We also investigate a solution for avoiding the unintended tuning (UT) and a
timing model to estimate the proper pulse width for memristance tuning. The simulation
results based on UMC 180nm technology and VTEAM model show the MemDE can
provide the delay between 0.55ns and 1.44ns which is compatible to the 4-bit multiplexerbased
delay element (MuxDE) in the same technology while consuming thirteen times
less power. The key contribution within (i) is the development of low-power MemDE to
mitigate the timing mismatch caused by PVT variations.
To estimate the temperature effect on memristance, we develop an empirical temperature
model which fits both titanium dioxide and silver chalcogenide memristors. The
temperature experiments are conducted using the latter device, and the results confirm
the validity of the proposed model with the accuracy R-squared >88%. The memristance
decoder is designed to deliver two key advantages. Firstly, the temperature model is
integrated into the VTEAM model to enable the temperature compensation. Secondly, it
supports resolution scalability to match the energy budget. The simulation results of the
2-bit decoder based on UMC 65nm technology show the energy can be varied between
49fJ and 98fJ. This is the second major contribution to address the challenge (ii).
This thesis gives future research directions into an in-depth study of the memristive
electronics as a variation-robust energy-efficient design paradigm and its impact on
developing future IoT applications.sponsored by the Royal Thai Governmen
Multiscaled simulation methodology for neuro-inspired circuits demonstrated with an organic memristor
International audienceOrganic memristors are promising molecular electronic devices for neuro-inspired on-chip learning applications. In this paper, we present a numerically efficient compact model suitable for Fe(bpy)2+3 organic memristors operating according to an intramolecular charge transfer switching mechanism. This compact model, being physics-based and relying on electrical characterizations and parametric extractions performed on test structures, is especially efficient in pulsed mode and describes the conductance variations for both SET and RESET regimes. Using this model, a dynamic multiscale simulation approach has been set-up to extend the model from individual devices to larger model systems that learn progressively through time. To verify the soundness and highlight emergent properties of the organic memristors, instances of the compact model have been simulated within a simple neuromorphic design that co-integrates with CMOS neurons. In addition, a larger supervised learning system using the new compact model is demonstrated. These successful tests suggest our model might be of interest to neuromorphic designers