Signal processing apparatus for multiplex transmission Patent

Sampling circuit for signal processing in multiplex transmission by Fourier analysi

Analysis of Internally Bandlimited Multistage Cubic-Term Generators for RF Receivers

Adaptive feedforward error cancellation applied to correct distortion arising from third-order nonlinearities in RF receivers requires low-noise low-power reference cubic nonidealities. Multistage cubic-term generators utilizing cascaded nonlinear operations are ideal in this regard, but the frequency response of the interstage circuitry can introduce errors into the cubing operation. In this paper, an overview of the use of cubic-term generators in receivers relative to other applications is presented. An interstage frequency response plan is presented for a receiver cubic-term generator and is shown to function for arbitrary three-signal third-order intermodulation generation. The noise of such circuits is also considered and is shown to depend on the total incoming signal power across a particular frequency band. Finally, the effects of the interstage group delay are quantified in the context of a relevant communication standard requirement

Depth-4 Lower Bounds, Determinantal Complexity : A Unified Approach

Tavenas has recently proved that any n^{O(1)}-variate and degree n polynomial in VP can be computed by a depth-4 circuit of size 2^{O(\sqrt{n}\log n)}. So to prove VP not equal to VNP, it is sufficient to show that an explicit polynomial in VNP of degree n requires 2^{\omega(\sqrt{n}\log n)} size depth-4 circuits. Soon after Tavenas's result, for two different explicit polynomials, depth-4 circuit size lower bounds of 2^{\Omega(\sqrt{n}\log n)} have been proved Kayal et al. and Fournier et al. In particular, using combinatorial design Kayal et al.\ construct an explicit polynomial in VNP that requires depth-4 circuits of size 2^{\Omega(\sqrt{n}\log n)} and Fournier et al.\ show that iterated matrix multiplication polynomial (which is in VP) also requires 2^{\Omega(\sqrt{n}\log n)} size depth-4 circuits. In this paper, we identify a simple combinatorial property such that any polynomial f that satisfies the property would achieve similar circuit size lower bound for depth-4 circuits. In particular, it does not matter whether f is in VP or in VNP. As a result, we get a very simple unified lower bound analysis for the above mentioned polynomials. Another goal of this paper is to compare between our current knowledge of depth-4 circuit size lower bounds and determinantal complexity lower bounds. We prove the that the determinantal complexity of iterated matrix multiplication polynomial is \Omega(dn) where d is the number of matrices and n is the dimension of the matrices. So for d=n, we get that the iterated matrix multiplication polynomial achieves the current best known lower bounds in both fronts: depth-4 circuit size and determinantal complexity. To the best of our knowledge, a \Theta(n) bound for the determinantal complexity for the iterated matrix multiplication polynomial was known only for constant d>1 by Jansen.Comment: Extension of the previous uploa

Pseudonoise code tracking loop

A delay-locked loop is presented for tracking a pseudonoise (PN) reference code in an incoming communication signal. The loop is less sensitive to gain imbalances, which can otherwise introduce timing errors in the PN reference code formed by the loop

Phase control circuits using frequency multiplications for phased array antennas

A phase control coupling circuit for use with a phased array antenna is described. The coupling circuit includes a combining circuit which is coupled to a transmission line, a frequency multiplier circuit which is coupled to the combining circuit, and a recombining circuit which is coupled between the frequency multiplier circuit and phased array antenna elements. In a doubler embodiment, the frequency multiplier circuit comprises frequency doublers and the combining and recombining circuits comprise four-port hybrid power dividers. In a generalized embodiment, the multiplier circuit comprises frequency multiplier elements which multiply to the Nth power, the combining circuit comprises four-part hybrid power dividers, and the recombinding circuit comprises summing circuits

New algorithms and lower bounds for circuits with linear threshold gates

Let $ACC \circ THR$ be the class of constant-depth circuits comprised of AND, OR, and MOD$m$ gates (for some constant $m > 1$), with a bottom layer of gates computing arbitrary linear threshold functions. This class of circuits can be seen as a "midpoint" between $ACC$ (where we know nontrivial lower bounds) and depth-two linear threshold circuits (where nontrivial lower bounds remain open). We give an algorithm for evaluating an arbitrary symmetric function of $2^{n^{o(1)}}$ $ACC \circ THR$ circuits of size $2^{n^{o(1)}}$, on all possible inputs, in $2^n \cdot poly(n)$ time. Several consequences are derived: $\bullet$ The number of satisfying assignments to an $ACC \circ THR$ circuit of subexponential size can be computed in $2^{n-n^{\varepsilon}}$ time (where $\varepsilon > 0$ depends on the depth and modulus of the circuit). $\bullet$ $NEXP$ does not have quasi-polynomial size $ACC \circ THR$ circuits, nor does $NEXP$ have quasi-polynomial size $ACC \circ SYM$ circuits. Nontrivial size lower bounds were not known even for $AND \circ OR \circ THR$ circuits. $\bullet$ Every 0-1 integer linear program with $n$ Boolean variables and $s$ linear constraints is solvable in $2^{n-\Omega(n/((\log M)(\log s)^{5}))}\cdot poly(s,n,M)$ time with high probability, where $M$ upper bounds the bit complexity of the coefficients. (For example, 0-1 integer programs with weights in $[-2^{poly(n)},2^{poly(n)}]$ and $poly(n)$ constraints can be solved in $2^{n-\Omega(n/\log^6 n)}$ time.) We also present an algorithm for evaluating depth-two linear threshold circuits (a.k.a., $THR \circ THR$) with exponential weights and $2^{n/24}$ size on all $2^n$ input assignments, running in $2^n \cdot poly(n)$ time. This is evidence that non-uniform lower bounds for $THR \circ THR$ are within reach