A novel time independent asynchronous communication protocol and its applications

This paper proposes a novel communications protocol called Time Independent Asynchronous (TIA) communications. This protocol constitutes a new category which has unique properties very useful in a variety of applications including embedded controller communications. The 2-wire TIA communications system proposed is implemented using software controlled IO. Analysis of this system shows that traditional Signal Transition Graphs (STGs) may fail to predict livelock and deadlock in software based systems. A modified form of STG called STG For Threads (STG-FT) is proposed to better model the behaviour of software driven systems and is shown to correctly detect livelock and deadlock that a normal STG model may miss. The performance of the new 2-wire TIA system is reported and livelock and deadlock properties found to match the STG-FT simulation. The new 2-wire TIA communication system has particular application to communications in products and industrial systems with low end microprocessors and any microprocessor that is heavily loaded with time critical applications

Multiple-valued multiple-rail encoding scheme for low-power asynchronous communication

科研費報告書収録論文(課題番号:15500029/研究代表者:羽生貴弘/双方向電流モード多値回路技術に基づく超高速非同期データ転送VLSIの開発

2-wire time independent asynchronous communications

Communications both to and between low end microprocessors represents a real cost in a number of industrial and consumer products. This thesis starts by examining the properties of protocols that help to minimize these expenses and comes to the conclusion that the derived set of properties define a new category of communications protocol : Time Independent Asynchronous ( TIA) communications. To show the utility of the TIA category we develop a novel TIA protocol that uses only 2-wires and general IO pins on each host. The protocol is analyzed using the Petri net based STG ( Signal Transition Graph) which is widely use to model asynchronous logic. It is shown that STGs do not accurately model the behavior of software driven systems and so a modified form called STG-FT ( STG For Threads) is developed to better model software systems. A simulator is created to take an STG-FT model and perform a full reachability tree analysis to prove correctness and analyze livelock and deadlock properties. The simulator can also examine the full reachability tree for every possible system state ( the cross product of all sub-system states), and analyze deadlock and livelock issues related to unexpected inputs and unusual situations. Reachability pruning algorithms are developed which decrease the search tree by a factor of approximately 250 million. The 2-wire protocol is implemented between a PC and an Atmel Tiny26 microprocessor, there is also a variant that works between microprocessors. Testing verifies the simulation results including an avoidable livelock condition with data throughput peaking at a useful 50 kilobits/second in both directions. The first practical application of 2-wire TIA is part of a novel debugger for the Atmel Tiny26 microprocessor. The approach can be extended to any microprocessor with general IO pins. TIA communications, developed in this thesis, is a serious contender whenever low end microprocessors must communicate with other processors. Consumer and industrial products may be able to achieve cost saving by using this new protocol