Energy-Aware Network-on-Chip Application Mapping Based on Domain Knowledge Genetic Algorithm

This paper addresses energy-aware application mapping for large-scale Network-on-chip (NoC). The increasing number of intellectual property (IP) cores in multi-processor system-on-chips (MPSoCs) makes NoC application mapping more challenging to find optimum core-to-topology mapping. This paper proposes an application mapping technique that incorporates domain knowledge into genetic algorithm (GA) to minimize the energy consumption of NoC communication. The GA is initialized with knowledge on network partition whereas the genetic crossover operator is guided with inter-core communication demands. NoC energy estimation is based on analytical energy model and cycle-accurate Noxim simulation. For large-scale NoC, application mapping using knowledge-based genetic operator saves up to 28% energy compared to the one on conventional GA. Adding knowledge-based initial mapping speeds up convergence by 81% and further saves energy by 5% compared to only knowledge-based crossover GA. Furthermore, cycle-accurate simulations of applications with traffic dependency show the effectiveness of the proposed application mapping for large-scale NoC

Memory-Aware Genetic Algorithms for Task Mapping on Hard Real-Time Networks-on-Chip

The problem of mapping hard real-time tasks onto networks-on-chip has previously been successfully addressed by genetic algorithms. However, none of the existing problem formulations consider memory constraints. State-of-the-art genetic mappers are therefore able to find fully-schedulable mappings which are incompatible with the memory limitations of realistic platforms. In this paper, we extend the problem formulation and devise a memory architecture, in the form of private local memories. We then propose three memory models of increasing complexity and realism, and evaluate the impact these additional constraints pose to the genetic search. We conduct extensive experiments using tasks and communications from a realistic benchmark application, and compare the proposed approach against a state-of-the-art baseline mapper

Анализ подходов к синтезу сетей на кристалле с использованием регулярных топологий

The article gives a review of existing methods of networks-on-chip design, based on the approach, in which the projection of the characteristic tasks graph is performed on a given regular topology. The general problem of the synthesis of networks-on-chip is characterized. The network topology can be foreknown (usually a regular topology) or selected in accordance with the tasks that will be performed by the network-on-chip. The first method of synthesis of networks-on-chip is widespread among the developers due to its relative simplicity and obviousness and presented in a variety of implementations, which are reviewed in this article. The advantages and disadvantages of this approach, the effect achieved by its application to various implementations of networks-on-chip and the way of its improvement, which is to extend the scope of solutions for regular network topologies on the predetermined irregular topologies with better characteristics are offered.В статье выполнен обзор существующих способов проектирования сетей на кристалле, основанных на подходе, при котором осуществляется проекция характеристического графа задачи на заданную регулярную топологию. Охарактеризована общая задача синтеза сетей на кристалле. Топология сети может быть заранее известной (обычно это регулярная топология) или выбирается в зависимости от задачи, которая будет выполняться сетью на кристалле. Первый способ синтеза сетей на кристалле благодаря своей относительной простоте и очевидности получил большое распространение среди разработчиков и представлен во множестве реализаций, обзор которых проведен в данной статье. Показаны преимущества и недостатки данного подхода, достигнутый эффект от его применения для различных реализаций сетей на кристалле, а также предложен путь его усовершенствования, который заключается в том, чтобы расширить область применения решений для регулярных топологий сетей на заранее заданные нерегулярные топологии с лучшими характеристиками

A Topology Design Customization Approach for STNoC

To support high bandwidth SoCs, a communication design flow is necessary for the design space exploration respecting tight design requirements. In order to exploit the benefits introduced by the NoC approach for the on-chip communication, the paper presents a design flow for the core mapping and customization of the network topology applied to STNoC, the Network on-Chip developed by STMicroelectronics. Starting from ring topology, the proposed application-specific flow tries to find a set of customized topologies, optimized in terms of performance and area/energy overhead, by adding links. The generated STNoC custom topologies provide a reduced cost with respect to the spidergon topology