Genetic algorithm approach to find the best input variable partitioning

Conference PaperThis paper presents a variable partition algorithm which combines the quasi-reduced ordered multiple-terminal multiple-valued decision diagrams and genetic algorithms (GAs). The algorithm is better than the previous techniques which find a good functional decomposition by non-exhaustive search and expands the range of searching for the best decomposition providing the optimal subtable multiplicity. The possible solutions are evaluated using the gain of decomposition for a multiple-output multiple-valued logic function. The distinct feature of GA is the possible solutions being coded by real numbers. Here the simplex-based crossover is proposed to use for the recombination stage of GA. It permits to increase the GA coverag

An overview of decision table literature 1982-1995.

This report gives an overview of the literature on decision tables over the past 15 years. As much as possible, for each reference, an author supplied abstract, a number of keywords and a classification are provided. In some cases own comments are added. The purpose of these comments is to show where, how and why decision tables are used. The literature is classified according to application area, theoretical versus practical character, year of publication, country or origin (not necessarily country of publication) and the language of the document. After a description of the scope of the interview, classification results and the classification by topic are presented. The main body of the paper is the ordered list of publications with abstract, classification and comments.

Decision diagrams in machine learning: an empirical study on real-life credit-risk data.

Decision trees are a widely used knowledge representation in machine learning. However, one of their main drawbacks is the inherent replication of isomorphic subtrees, as a result of which the produced classifiers might become too large to be comprehensible by the human experts that have to validate them. Alternatively, decision diagrams, a generalization of decision trees taking on the form of a rooted, acyclic digraph instead of a tree, have occasionally been suggested as a potentially more compact representation. Their application in machine learning has nonetheless been criticized, because the theoretical size advantages of subgraph sharing did not always directly materialize in the relatively scarce reported experiments on real-world data. Therefore, in this paper, starting from a series of rule sets extracted from three real-life credit-scoring data sets, we will empirically assess to what extent decision diagrams are able to provide a compact visual description. Furthermore, we will investigate the practical impact of finding a good attribute ordering on the achieved size savings.Advantages; Classifiers; Credit scoring; Data; Decision; Decision diagrams; Decision trees; Empirical study; Knowledge; Learning; Real life; Representation; Size; Studies;

Synthesis and Optimization of Reversible Circuits - A Survey

Reversible logic circuits have been historically motivated by theoretical research in low-power electronics as well as practical improvement of bit-manipulation transforms in cryptography and computer graphics. Recently, reversible circuits have attracted interest as components of quantum algorithms, as well as in photonic and nano-computing technologies where some switching devices offer no signal gain. Research in generating reversible logic distinguishes between circuit synthesis, post-synthesis optimization, and technology mapping. In this survey, we review algorithmic paradigms --- search-based, cycle-based, transformation-based, and BDD-based --- as well as specific algorithms for reversible synthesis, both exact and heuristic. We conclude the survey by outlining key open challenges in synthesis of reversible and quantum logic, as well as most common misconceptions.Comment: 34 pages, 15 figures, 2 table

Применение диаграмм решений не полностью определенных функций k-значной логики при синтезе логических схем

Objectives. The problem of circuit implementation of incompletely specified (partial) k-valued logic functions given by tabular representations is considered. The stage of technologically independent optimization is studied to obtain minimized representations of systems of completely specified Boolean functions from tabular representations of partial functions of k-valued logic. According to these representations of Boolean functions, technological mapping is performed at the second stage of the synthesis of logic circuits.Methods. Using additional definitions of Multi-valued Decision Diagrams (MDD) representing partial functions of k-valued logic, and Binary Decision Diagrams (BDD) representing partial systems of Boolean functions at the stage of technologically independent optimization is proposed. The task of additional definition of MDD is oriented to reducing the number of vertices of the MDD graph that correspond to the cofactors of the Shannon expansion of a multi-valued function.Results. The MDD minimization problem is reduced to solving the problems of coloring undirected graphs of incompatibility of cofactors by minimum number of colors. Encoding of multi-valued values of arguments and values of functions of k-valued logic by binary codes leads to systems of partial Boolean functions, which are also further defined in order to minimize their multi-level BDD representations.Conclusion. The proposed approach makes it possible to define partial multi-valued functions to fully defined Boolean functions in two stages. At the second stage, well-known and effective methods are used to redefine BDD representing systems of partial Boolean functions. As a result of this two-step approach, minimized BDD representations of systems of completely defined functions are obtained. According to completely defined Boolean functions, a technological mapping into a given library of logical elements is performed, i.e. the optimized descriptions of Boolean function systems are covered with descriptions of logical elementsЦели. Рассматривается проблема схемной реализации не полностью определенных функций k-значной логики, заданных табличными представлениями. Изучается этап технологически независимой оптимизации. Целью этого этапа является получение по табличным представлениям не полностью определенных функций k-значной логики минимизированных представлений систем полностью определенных булевых функций, по которым выполняется технологическое отображение (technology mapping) – второй этап синтеза логических схем.Методы. При синтезе логических схем на этапе технологически независимой оптимизации предлагается использовать доопределения многозначных диаграмм решений (Reduced Ordered Multi-valued Decision Diagrams, ROMDD), которые далее называются MDD, и доопределения бинарных диаграмм решений (Binary Decision Diagram, BDD), задающих не полностью определенные системы булевых функций. Доопределение MDD ориентировано на уменьшение числа вершин графа MDD, соответствующих кофакторам разложения Шеннона многозначной функции.Результаты. Задача минимизации MDD сведена к решению задач минимальной раскраски неориентированных графов несовместимости кофакторов. Кодирование многозначных значений аргументов и значений функций k-значной логики двоичными кодами приводит к системам не полностью определенных булевых функций, которые также доопределяются с целью минимизации их многоуровневых BDD-представлений.Заключение. Предложенный подход позволяет в два этапа провести доопределение частичных многозначных функций до полностью определенных булевых функций. На втором этапе используются известные и эффективные методы доопределения BDD, задающих системы не полностью определенных булевых функций. В результате такого двухэтапного подхода получаются минимизированные BDD-представления систем полностью определенных функций. По полностью определенным булевым функциям выполняется технологическое отображение в заданную библиотеку логических элементов, т. е. покрытие оптимизированных описаний систем булевых функций описаниями логических элементов

Combinational multiple-valued circuit design by generalised disjunctive decomposition

A design of multiple-valued circuits based on the multiple-valued programmable logic arrays (MV PLA’s) by generalized disjunctive decomposition is presented. Main subjects are 1) Generalized disjunctive decomposition of multiple-valued functions using multiple-terminal multiplevalued decision diagrams (MTMDD’s); 2) Realization of functions by MV PLA-based combinatorial circuits