Compact and Efficient Millimetre-Wave Circuits for Wideband Applications

Radio systems, along with the ever increasing processing power provided by computer technology, have altered many aspects of our society over the last century. Various gadgets and integrated electronics are found everywhere nowadays; many of these were science-fiction only a few decades ago. Most apparent is perhaps your ``smart phone'', possibly kept within arm's reach wherever you go, that provides various services, news updates, and social networking via wireless communications systems. The frameworks of the fifth generation wireless system is currently being developed worldwide. Inclusion of millimetre-wave technology promise high-speed piconets, wireless back-haul on pencil-beam links, and further functionality such as high-resolution radar imaging. This thesis addresses the challenge to provide signals at carrier frequencies in the millimetre-wave spectrum, and compact integrated transmitter front-ends of sub-wavelength dimensions. A radio frequency pulse generator, i.e. a ``wavelet genarator'', circuit is implemented using diodes and transistors in III--V compound semiconductor technology. This simple but energy-efficient front-end circuit can be controlled on the time-scale of picoseconds. Transmission of wireless data is thereby achieved at high symbol-rates and low power consumption per bit. A compact antenna is integrated with the transmitter circuit, without any intermediate transmission line. The result is a physically small, single-chip, transmitter front-end that can output high equivalent isotropically radiated power. This element radiation characteristic is wide-beam and suitable for array implementations

Design Techniques for Energy Efficient Multi-GB/S Serial I/O Transceivers

Total I/O bandwidth demand is growing in high-performance systems due to the emergence of many-core microprocessors and in mobile devices to support the next generation of multi-media features. High-speed serial I/O energy efficiency must improve in order to enable continued scaling of these parallel computing platforms in applications ranging from data centers to smart mobile devices. The first work, a low-power forwarded-clock I/O transceiver architecture is presented that employs a high degree of output/input multiplexing, supply-voltage scaling with data rate, and low-voltage circuit techniques to enable low-power operation. The transmitter utilizes a 4:1 output multiplexing voltage-mode driver along with 4-phase clocking that is efficiently generated from a passive poly-phase filter. The output driver voltage swing is accurately controlled from 100-200 mV_(ppd) using a low-voltage pseudo-differential regulator that employs a partial negative-resistance load for improved low frequency gain. 1:8 input de-multiplexing is performed at the receiver equalizer output with 8 parallel input samplers clocked from an 8-phase injection-locked oscillator that provides more than 1UI de-skew range. Low-power high-speed serial I/O transmitters which include equalization to compensate for channel frequency dependent loss are required to meet the aggressive link energy efficiency targets of future systems. The second work presents a low power serial link transmitter design that utilizes an output stage which combines a voltage-mode driver, which offers low static-power dissipation, and current-mode equalization, which offers low complexity and dynamic-power dissipation. The utilization of current-mode equalization decouples the equalization settings and termination impedance, allowing for a significant reduction in pre-driver complexity relative to segmented voltage-mode drivers. Proper transmitter series termination is set with an impedance control loop which adjusts the on-resistance of the output transistors in the driver voltage-mode portion. Further reductions in dynamic power dissipation are achieved through scaling the serializer and local clock distribution supply with data rate. Finally, it presents that a scalable quarter-rate transmitter employs an analog-controlled impedance-modulated 2-tap voltage-mode equalizer and achieves fast power-state transitioning with a replica-biased regulator and ILO clock generation. Capacitively-driven 2 mm global clock distribution and automatic phase calibration allows for aggressive supply scaling

Design and Development of a Multi-Purpose Input Output Controller Board for the SPES Control System

This PhD work has been carried out at the Legnaro National Laboratories (LNL), one of the four national labs of the National Institute for Nuclear Physics (INFN). The mission of LNL is to perform research in the field of nuclear physics and nuclear astrophysics together with emerging technologies. Technological research and innovation are the key to promote excellence in science, to excite competitive industries and to establish a better society. The research activities concerning electronics and computer science are an essential base to develop the control system of the Selective Production of Exotic Species (SPES) project. Nowadays, SPES is the most important project commissioned at LNL and represents the future of the Lab. It is a second generation Isotope Separation On-Line (ISOL) radioactive ion beam facility intended for fundamental nuclear physics research as well as experimental applications in different fields of science, such as nuclear medicine; radio-pharmaceutical production for therapy and diagnostic. The design of the SPES control system demands innovative technologies to embed the control of several appliances with different requirements and performing different tasks spanning from data sharing and visualization, data acquisition and storage, networking, security and surveillance operations, beam transport and diagnostic. The real time applications and fast peripherals control commonly found in the distributed control network of particle accelerators are accompanied by the challenge of developing custom embedded systems. In this context, the proposed PhD work describes the design and development of a multi-purpose Input Output Controller (IOC) board capable of embedding the control of typical accelerator instrumentation involved in the automatic beam transport system foreseen for the SPES project. The idea behind this work is to extend the control reach to the single device level without losing in modularity and standardization. The outcome of the research work is a general purpose embedded computer that will be the base for standardizing the hardware layer of the frontend computers in the SPES distributed control system. The IOC board is a Computer-on-Module (COM) carrier board designed to host any COM Express type 6 module and is equipped with a Field Programmable Gate Array (FPGA) and user application specific I/O connection solutions not found in a desktop pc. All the generic pc functionalities are readily available in off-the-shelf modules and the result is a custom motherboard that bridges the gap between custom developments and commercial personal computers. The end user can deal with a general-purpose pc with a high level of hardware abstraction besides being able to exploit the on-board FPGA potentialities in terms of fast peripherals control and real time digital data processing. This document opens with an introductory chapter about the SPES project and its control system architecture and technology before to describe the IOC board design, prototyping, and characterization. The thesis ends describing the installation in the field of the IOC board which is the core of the new diagnostics data readout and signal processing system. The results of the tests performed under real beam conditions prove that the new hardware extends the current sensitivity to the pA range, addressing the SPES requirements, and prove that the IOC board is a reliable solution to standardize the control of several appliances in the SPES accelerators complex where it will be embedded into physical equipment, or in their proximity, and will control and monitor their operation replacing the legacy VME technology. The installation in the field of the IOC board represents a great personal reward and crowns these years of busy time during which I turned what was just an idea in 2014, into a working embedded computer today

An FPGA based topological processor prototype for the ATLAS Level-1 trigger upgrade

By 2014 the LHC will collide proton bunches at 14TeV with an increased instantaneous luminosity up to 3·10³⁴cm⁻²s⁻¹. The resulting higher event rate will challenge the existing ATLAS trigger system. A reduction on the trigger rate can be achieved by selecting interesting channels based on their expected decay topology and thus reducing background. This will be achieved by introducing of a new FPGA based module in the Level-1 trigger: the Topological Processor L1Topo. With L1Topo it will be possible for the first time to concentrate detailed information from the entire calorimeters and the muon detector into a single module. L1Topo will receive a total aggregate bandwidth of 1Tb/s. The data is processed within less than 100ns, requiring high density optical I/O and high bandwidth, which is achieved by adopting state-of-the-art FPGAs with embedded multi-Gb/s transceivers and multi-Gb/s opto converters. This paper focuses on the design of the first L1Topo prototype. The L1Topo design adopts technologies that have been implemented into a previous ATCA form factor demonstrator module. The latest results on the implementation of a topological algorithm in the demonstrator module and FPGA logic utilization of the algorithm are presented. Beyond results of a measurement of the latency, induced by the demonstrator module's FPGA's integrated Multi-Gb/s transceivers, are reported