2 research outputs found
200 Gb/s transmission using a dual-polarization O-Band silicon photonic intensity modulator for Stokes vector direct detection applications
We present a dual-polarization O-band silicon photonic (SiP) transmitter for intra-datacenter optical interconnects. The transmitter is built using two identical O-band traveling wave Mach-Zehnder modulators with an average VπL and a bandwidth at 1.5 V bias voltage of 2.88 V.cm and 24.5 GHz, respectively. We experimentally demonstrate the transmitter in a Stokes vector direct-detection (SV-DD) system for dual-polarization intensity modulated signals with 2-level and 4-level pulse amplitude modulation (DP-PAM2 and DP-PAM4) formats. The direct-detection Stokes vector receiver (DD-SVR) followed by offline digital signal processing (DSP) is implemented for SOP de-rotation. We characterize the performance of the SV-DD system versus number of taps, received signal power, state of polarization (SOP), reach, and bit rate. Results reveal that 112 Gb/s DP-PAM2 can be transmitted over 10 km of single mode fiber (SMF) at a bit error rate (BER) below 10−5 at −1 dBm received signal power irrespective of the SOP. Moreover, a 168 Gb/s (42 Gbaud) DP-PAM4 signal can be transmitted over 2 km and 10 km at a BER below the 7% hard-decision forward error correction (HD-FEC) threshold (i.e., 3.8 × 10−3) at 0 dBm and 2 dBm, respectively. Furthermore, 224 Gb/s and 200 Gb/s DP-PAM4 are successfully received at a BER below the HD-FEC in the back-to-back and 2 km cases, respectively. Finally, we compare the performance of the 6 × 2 multiple-input multiple-output (MIMO) equalization to a simpler 4 × 2 MIMO equalization and explain the superior performance of the 6 × 2 in the presence of SVR imperfections
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Development of Silicon Photonic Multi Chip Module Transceivers
The exponential growth of data generation–driven in part by the proliferation of applications such as high definition streaming, artificial intelligence, and the internet of things–presents an impending bottleneck for electrical interconnects to fulfill data center bandwidth demands. Links now require bandwidths in excess of multiple Tbps while operating on the order of picojoules per bit, in addition to constraints on areal bandwidth densities and pin I/O bandwidth densities. Optical communications built on a silicon photonic platform offers a potential solution to develop power efficient, high bandwidth, low attenuation, small footprint links, all while building off the mature CMOS ecosystem. The development of silicon photonic foundries supporting multi project wafer runs with associated process design kit components supports a path towards widespread commercial production by increasing production volume while reducing fabrication and development costs. While silicon photonics can always be improved in terms of performance and yield, one of the central challenges is the integration of the silicon photonic integrated circuits with the driving electronic integrated circuits and data generating compute nodes such as CPUs, FPGAs, and ASICs. The co-packaging of the photonics with the electronics is crucial for adoption of silicon photonics in datacenters, as improper integration negates all the potential benefits of silicon photonics.
The work in this dissertation is centered around the development of silicon photonic multi chip module transceivers to aid in the deployment of silicon photonics within data centers. Section one focuses on silicon photonic integration and highlights multiple integrated transceiver prototypes. The central prototype features a photonic integrated circuit with bus waveguides with WDM microdisk modulators for the transmitter and WDM demuxes with drop ports to photodiodes for the receiver. The 2.5D integrated prototype utilizes a thinned silicon interposer and TIA electronic integrated circuits. The architecture, integration, characterization, performance, and scalability of the prototype are discussed. The development of this first prototype identified key design considerations necessary for designing multi chip module silicon photonic prototypes, which will be addressed in this section. Finally, other multi chip module silicon photonic prototypes will be overviewed. These include a 2.5D integrated transceiver with a different electronic integrated circuit TIA, a 3D integrated receiver, an active interposer network on chip, and a 2.5D integrated transceiver with custom electronic integrated circuits. Section two focuses on research that supports the development of silicon photonic transceivers. The thermal crosstalk from neighboring microdisk modulators as a function of modulator pitch is investigated. As modulators are placed at denser pitches to accommodate areal bandwidth density requirements in transceivers, this thermal crosstalk will become significant. In this section, designs and results from several iterations of custom microring modulators are reported. Custom microring modulators allow for scaling up the number of channels in microring transceivers by offering the ability to fabricate variable resonances and provide a platform for further innovation in bandwidth, free spectral range, and energy efficiency. The designs and results of higher order modulation format modulators, both microring based and Mach Zehnder based, are discussed. High order modulators offer a path towards scaling transceiver total throughput without having to increase the channel counts or component bandwidth. Together, the work in these two sections supports the development of silicon photonic transceivers to aid in the adoption of silicon photonics into data generating systems