CAD methodologies for low power and reliable 3D ICs

The main objective of this dissertation is to explore and develop computer-aided-design (CAD) methodologies and optimization techniques for reliability, timing performance, and power consumption of through-silicon-via(TSV)-based and monolithic 3D IC designs. The 3D IC technology is a promising answer to the device scaling and interconnect problems that industry faces today. Yet, since multiple dies are stacked vertically in 3D ICs, new problems arise such as thermal, power delivery, and so on. New physical design methodologies and optimization techniques should be developed to address the problems and exploit the design freedom in 3D ICs. Towards the objective, this dissertation includes four research projects. The first project is on the co-optimization of traditional design metrics and reliability metrics for 3D ICs. It is well known that heat removal and power delivery are two major reliability concerns in 3D ICs. To alleviate thermal problem, two possible solutions have been proposed: thermal-through-silicon-vias (T-TSVs) and micro-fluidic-channel (MFC) based cooling. For power delivery, a complex power distribution network is required to deliver currents reliably to all parts of the 3D IC while suppressing the power supply noise to an acceptable level. However, these thermal and power networks pose major challenges in signal routability and congestion. In this project, a co-optimization methodology for signal, power, and thermal interconnects in 3D ICs is presented. The goal of the proposed approach is to improve signal, thermal, and power noise metrics and to provide fast and accurate design space explorations for early design stages. The second project is a study on 3D IC partition. For a 3D IC, the target circuit needs to be partitioned into multiple parts then mapped onto the dies. The partition style impacts design quality such as footprint, wirelength, timing, and so on. In this project, the design methodologies of 3D ICs with different partition styles are demonstrated. For the LEON3 multi-core microprocessor, three partitioning styles are compared: core-level, block-level, and gate-level. The design methodologies for such partitioning styles and their implications on the physical layout are discussed. Then, to perform timing optimizations for 3D ICs, two timing constraint generation methods are demonstrated that lead to different design quality. The third project is on the buffer insertion for timing optimization of 3D ICs. For high performance 3D ICs, it is crucial to perform thorough timing optimizations. Among timing optimization techniques, buffer insertion is known to be the most effective way. The TSVs have a large parasitic capacitance that increases the signal slew and the delay on the downstream. In this project, a slew-aware buffer insertion algorithm is developed that handles full 3D nets and considers TSV parasitics and slew effects on delay. Compared with the well-known van Ginneken algorithm and a commercial tool, the proposed algorithm finds buffering solutions with lower delay values and acceptable runtime overhead. The last project is on the ultra-high-density logic designs for monolithic 3D ICs. The nano-scale 3D interconnects available in monolithic 3D IC technology enable ultra-high-density device integration at the individual transistor-level. The benefits and challenges of monolithic 3D integration technology for logic designs are investigated. First, a 3D standard cell library for transistor-level monolithic 3D ICs is built and their timing and power behavior are characterized. Then, various interconnect options for monolithic 3D ICs that improve design quality are explored. Next, timing-closed, full-chip GDSII layouts are built and iso-performance power comparisons with 2D IC designs are performed. Important design metrics such as area, wirelength, timing, and power consumption are compared among transistor-level monolithic 3D, gate-level monolithic 3D, TSV-based 3D, and traditional 2D designs.PhDCommittee Chair: Lim, Sung Kyu; Committee Member: Bakir, Muhannad; Committee Member: Kim, Hyesoon; Committee Member: Lee, Hsien-Hsin; Committee Member: Mukhopadhyay, Saiba

3-Dimensional Tuning of an Atomically Defined Silicon Tunnel Junction

A requirement for quantum information processors is the in-situ tunability of the tunnel rates and the exchange interaction energy within the device. The large energy level separation for atom qubits in silicon is well suited for qubit operation but limits device tunability using in-plane gate architectures, requiring vertically separated top-gates to control tunnelling within the device. In this paper we address control of the simplest tunnelling device in Si:P, the tunnel junction. Here we demonstrate that we can tune its conductance by using a vertically separated top-gate aligned with +-5nm precision to the junction. We show that a monolithic 3D epitaxial top-gate increases the capacitive coupling by a factor of 3 compared to in-plane gates, resulting in a tunnel barrier height tunability of 0-186meV. By combining multiple gated junctions in series we extend our monolithic 3D gating technology to implement nanoscale logic circuits including AND and OR gates

Method to make a single-step etch mask for 3D monolithic nanostructures

Current nanostructure fabrication by etching is usually limited to planar structures as they are defined by a planar mask. The realisation of three-dimensional (3D) nanostructures by etching requires technologies beyond planar masks. We present a method to fabricate a 3D mask that allows to etch three-dimensional monolithic nanostructures by using only CMOS-compatible processes. The mask is written in a hard-mask layer that is deposited on two adjacent inclined surfaces of a Si wafer. By projecting in single step two different 2D patterns within one 3D mask on the two inclined surfaces, the mutual alignment between the patterns is ensured. Thereby after the mask pattern is defined, the etching of deep pores in two oblique directions yields a three-dimensional structure in Si. As a proof of concept we demonstrate 3D mask fabrication for three-dimensional diamond-like photonic band gap crystals in silicon. The fabricated crystals reveal a broad stop gap in optical reflectivity measurements. We propose how 3D nanostructures with five different Bravais lattices can be realised, namely cubic, tetragonal, orthorhombic, monoclinic, and hexagonal, and demonstrate a mask for a 3D hexagonal crystal. We also demonstrate the mask for a diamond-structure crystal with a 3D array of cavities. In general, the 2D patterns for the different surfaces can be completely independent and still be in perfect mutual alignment. Indeed, we observe an alignment accuracy of better than 3.0 nm between the 2D mask patterns on the inclined surfaces, which permits one to etch well-defined monolithic 3D nanostructures.Comment: 18 pages, 10 figure