Impact of the technology boosters on the MOSFET performance

The understanding of the charge transport in nano-scale CMOS device is a very challenging issue that requires a physics-based modelling approach. I use a Multi Subband Monte Carlo simulation framework to assess the effects of some of the mostly used techniques to overcome the performances of the conventional ultra-scaled MOSFET

Investigation of the electrical properties of Si₁-×Ge× channel pMOSFETs with high-κ dielectrics

It is now apparent that the continued performance enhancements of silicon metal-oxide-semiconductor field effect transistors (MOSFETs) can no longer be met by scaling alone. High-mobility channel materials such as strained Si1-xGex and Ge are now being seriously considered to maintain the performance requirements specified by the semiconductor industry. In addition, alternative gate dielectric, or high-κ dielectrics, will also be required to meet gate leakage requirements. This work investigates the properties of using strained Si1-xGex or Ge as alternative channel materials for pMOSFETs incorporating hafnium oxide (HfO2) high-κ gate dielectric. Whilst the SiGe pMOSFETs (x = 0.25) exhibited an enhancement in hole mobility (300 K) over comparable silicon control pMOSFETs with sputtered HfO2 dielectric, high Coulomb scattering and surface roughness scattering relating to the dielectric deposition process meant that the effective hole mobilities were degraded with respect to the silicon universal curve. Germanium channel pMOSFETs with halo-doping and HfO2 gate dielectric deposited by atomic layer deposition showed high hole mobilities of 230 cm2V-1s-1 and 480 cm2V-1s-1 at room temperature and 77 K, respectively. Analysis of the off-state current for the Ge pMOSFETs over a range of temperatures indicated that band-to-band tunnelling, gate-induced drain leakage and other defect-assisted leakage mechanisms could all be important. Hole carrier velocity and impact ionisation were also studied in two batches of buried channel SiGe pMOSFET with x = 0.15 and x = 0.36, respectively. SiGe channel pMOSFETs were found to exhibit reduced impact ionisation compared to silicon control devices, which has been attributed to a strain-induced reduction of the density of states in the SiGe conduction and valence bands. Analysis of the hole carrier velocity indicated that pseudomorphic SiGe offered no performance enhancements over Si below 100 nm, possibly due to higher ion implantation damage and strain relaxation of the strained SiGe channel. The results indicate that velocity overshoot effects might not provide the performance improvements at short channel lengths that was previously hoped for

Numerical simulation of sub-100 nm strained Si/SiGe MOSFETs for RF and CMOS applications

Drift-Diffusion, Hydrodynamic and Monte Carlo simulations have been used in this work to simulate strained Si/SiGe devices for RF and CMOS applications. For numerical simulations of Si/SiGe devices, strain effects on the band structure of Si have been analyzed and analytical expressions are presented for parameters related to the bandgap and band alignment of Si/SiGe heterostructure. Optimization of n-type buried strained Si channel Si/SiGe MODFETs has been carried out in order to achieve high RF performance and high linearity. The impact of both lateral and vertical device geometries and different doping strategies has been investigated. The impact of the Ge content of the SiGe buffer on the performance of p-type surface channel strained Si/SiGe MOSFETs has been studied. Hydrodynamic device simulations have been used to assess the device performance of p-type strained Si/SiGe MOSFETs down to 35 nm gate lengths. Well-tempered strained Si MOSFETs with halo implants around the source/drain regions have been simulated and compared with those devices possessing only a single retrograde channel doping. The calibrations in respect of sub-100 nm Si and strained Si MOSFETs fabricated by IBM lead to a scaling study of those devices at 65 nm, 45 nm and 35 nm gate lengths. Using Drift-Diffusion simulations, ring oscillator circuit behaviour has been evaluated. Strained Si on insulator (SSOI) circuits have also been simulated and compared with strained Si circuits, Si circuits employing conventional surface channel MOSFETs along with SOI devices. Ensemble Monte Carlo simulations have been used to evaluate the device performance of n-type strained Si MOSFETs. A non-perturbative interface roughness scattering model has been used and validated by calibrating with respect to experimental mobility behaviour and device characteristics. The impact of interface roughness on the performance enhancement of strained Si MOSFETs has been investigated and evidence for reduced interface roughness scattering is presented, i.e., a smoother interface is suggested in strained Si MOSFETs. A 35 nm gate length Toshiba Si MOSFET has been simulated and the performance enhancement of 35 nm strained Si MOSFETs over the Toshiba Si device is predicted. Monte Carlo simulations are also employed to investigate the performance degradation due to soft-optical phonon scattering, which arises with the introduction of high-K gate dielectrics. Based on the device structures of the calibrated sub-100 nm n-type conventional and strained Si IBM MOSFETs, significant current degradation has been observed in devices with high-K gate dielectrics, HfO2 and Al2O3

Characterization of negative bias temperature instability and lifetime prediction for pMOSFETs

In order to achieve high speed and packing density, the size of the transistor has shrunk aggressively. The gate dielectric, as the most critical component in the transistor, is undergoing rapid and substantial changes with the adoption of ultra-thin plasma nitrided oxide and more recently high-k dielectrics. As the nitrogen concentration in silicon oxynitrides (SiON) increases, the negative bias temperature instability (NBTI) rises and becomes a limiting factor for device lifetime. The NBTI can recover significantly during typical measurement time when using conventional instruments. To suppress this recovery, several fast techniques have been developed, including ultra-fast pulse Id-Vgtechnique and the On-The-Fly technique. These techniques, however, give different threshold voltage degradation (~VI) after the same stress. The interpretation of this difference is still controversial. The objective of chapter 3 is to bridge the gap between the ~Vt extracted from these techniques. Degradation and recovery during measurement, measurement and truncation errors, and evaluation of transconductance are examined. After taking these factors into account, the gap in llVt still cannot be filled. The effect of the sensing Vg on l::,.Vits considered and it is found that 111VtinI creases with sensing IVgl.The popular assumption of t:.Vt being independent of sensing Vg is invalid, thereafter. After taking both the effect of sensing Vg and recovery into account, the gap in llVt is successfully bridged. The difference between the effect of sensing Vg and recovery is explored, and the results show that they are two different phenomena. The recovery suppression and the sensing Vg effect challenge the applicability of the traditional lifetime prediction technique. In a large circuit with roughly 106 MOSFETs, there will always be some of them under the worst case condition, namely constant stress without recovery. The failure of one of these MOSFETs can lead to the malfunction of the whole circuit. At present, there is little information on how this worst case NBTI lifetime can be predicted and whether the traditional Vg acceleration technique can be applied. In chapter 4, the worst case lifetime prediction is investigated. It is found that the prediction based on the Vg acceleration results in substantial errors. To predict the worst-case lifetime, a model for NBTI kinetics under operation gate bias is developed. This kinetics includes contributions from both as-grown and generated defects and it no longer follows a simple power law. Based on the new kinetics, a single test prediction method is proposed and its safety margin is estimated to be 50%. Mobility reduction is another important issue when oxide thickness becomes thinner. It is reported that when the gate SiON becomes thinner than 2 nm or the interfacial layer in high-k stack is thinner than 2.5 nm, carrier mobility reduces. Agreement has not yet been reached on the level of reduction, or on the underlying mechanism. Remote charge scattering (ReS) has been proposed to be responsible for this mobility reduction. However, one weakness of earlier work is that different samples were used when experimentally studying the Res and this introduces uncertainties. For example, a reduction in oxide thickness does not only bring the gate closer to the substrate, but also modulates other factors such as surface roughness. In chapter 5, the importance of ReS is assessed by varying charge in the same device through either processing or electron trapping, to remove the uncertainties from using different devices. It is found that by increasing charge density at 0.56 - 1 nm from the substrate interface to the order of 1020 ern", both electron and hole mobility change little

Caractérisation électrique et modélisation des transistors FDSOI sub-22nm

Silicon on insulator (SOI) transistors are among the best candidates for sub-22nm technology nodes. At this scale, the devices integrate extremely thin buried oxide layers (BOX) and body. They also integrate advanced high-k dielectric / metal gate stacks and strain engineering is used to improve transport properties with, for instance, the use of SiGe alloys in the channel of p-type MOS transistors. The optimization of such a technology requires precise and non-destructive experimental techniques able to provide information about the quality of electron transport and interface quality, as well as about the real values of physical parameters (dimensions and doping level) at the end of the process. Techniques for parameter extraction from electrical characteristics have been developed over time. The aim of this thesis work is to reconsider these methods and to further develop them to account for the extremely small dimensions used for sub-22nm SOI generations. The work is based on extended characterization and modelling in support. Among the original results obtained during this thesis, special notice should be put on the adaptation of the complete split CV method which is now able to extract the characteristic parameters for the entire stack, from the substrate and its doping level to the gate stack, as well as an extremely detailed analysis of electron transport based on low temperature characterization in back-gate electrostatic coupling conditions or the exploitation of channel magnetoresistance from the linear regime of operation to saturation. Finally, a detailed analysis of low-frequency noise closes this study.Parmi les architectures candidates pour les générations sub-22nm figurent les transistors sur silicium sur isolant (SOI). A cette échelle, les composants doivent intégrer des films isolants enterrés (BOX) et des canaux de conduction (Body) ultra-minces. A ceci s'ajoute l'utilisation d'empilements de grille avancés (diélectriques à haute permittivité / métal de grille) et une ingénierie de la contrainte mécanique avec l'utilisation d'alliages SiGe pour le canal des transistors de type P. La mise au point d'une telle technologie demande qu'on soit capable d'extraire de façon non destructive et avec précision la qualité du transport électronique et des interfaces, ainsi que les valeurs des paramètres physiques (dimensions et dopages), qui sont obtenues effectivement en fin de fabrication. Des techniques d'extraction de paramètres ont été développées au cours du temps. L'objectif de cette thèse est de reconsidérer et de faire évoluer ces techniques pour les adapter aux épaisseurs extrêmement réduites des composants étudiés. Elle combine mesures approfondies et modélisation en support. Parmi les résultats originaux obtenus au cours de cette thèse, citons notamment l'adaptation de la méthode split CV complète qui permet désormais d'extraire les paramètres caractérisant l'ensemble de l'empilement SOI, depuis le substrat et son dopage jusqu'à la grille, ainsi qu'une analyse extrêmement détaillée du transport grâce à des mesures en régime de couplage grille arrière à température variable ou l'exploitation de la magnétorésistance de canal depuis le régime linéaire jusqu'en saturation. Le mémoire se termine par une analyse détaillée du bruit basse fréquence

Extended models of Coulomb scattering for the Monte Carlo simulation of nanoscale silicon MOSFETs

The International Technology Roadmap for Semiconductors (ITRS) specifies that MOSFET logic devices are to be scaled to sub-10nm dimensions by the year 2020, with 32nm bulk devices ready for production and double-gate FinFET devices demonstrated down to 5nm channel lengths. Future device generations are expected to have lower channel doping in order to reduce variability in devices due to the discrete nature of the channel dopants. Accompanying the reduced channel doping is a corresponding increase in the screening length, which is even now comparable with the channel length. Under such conditions, Coulomb scattering mechanisms become increasingly complex as the scattering potential interacts with a larger proportion of the device. Ionized impurity scattering within the channel is known to be an important Coulombic scattering mechanism within MOSFETs. Those channel impurities located close to the heavily doped source and drain or both, will induce a polarisation charge within the source and drain. These polarisation charge effects are shown in this work to increase the net screening of the channel impurities, due to the inclusion of remote screening effects, and significantly decrease the scattering rate associated with ionized impurity scattering. Remote screening can potentially reduce the control by ionized channel impurities over channel transport properties, leading to an increased sub-threshold current. A potential model has been obtained that is based on an exact solution of Poisson’s equation for an ionized impurity located close to one or both of these highly doped contact regions. The model shows that remote screening effects are evident within a few channel screening lengths of the highly doped contact regions. The resultant scattering model developed from this potential, which is based on the Born approximation, is implemented within a Monte Carlo simulator and is applied to MOSFET device simulation. The newly developed ionized impurity scattering model, which allows for remote screening, is applied in the simulation of two representative MOSFET devices: the first device being a bulk MOSFET device developed for the 32nm technology generation; the second device is an Ultra-Thin-Body Double Gate (UTB DG) MOSFET developed for the forthcoming 22nm technology generation. Thorough investigative simulations show that for both the bulk MOSFET and the UTB DG MOSFET, that remote screening of channel impurities in these devices is not a controlling effect. These results prove that the current model for ionized impurity scattering employed in Monte Carlo simulations is sufficient to model devices scaled to at least the 22nm technology node, predicted to be in production in the year 2012

Simulation study of scaling design, performance characterization, statistical variability and reliability of decananometer MOSFETs

This thesis describes a comprehensive, simulation based scaling study – including device design, performance characterization, and the impact of statistical variability – on deca-nanometer bulk MOSFETs. After careful calibration of fabrication processes and electrical characteristics for n- and p-MOSFETs with 35 nm physical gate length, 1 nm EOT and stress engineering, the simulated devices closely match the performance of contemporary 45 nm CMOS technologies. Scaling to 25 nm, 18 nm and 13 nm gate length n and p devices follows generalized scaling rules, augmented by physically realistic constraints and the introduction of high-k/metal-gate stacks. The scaled devices attain the performance stipulated by the ITRS. Device a.c. performance is analyzed, at device and circuit level. Extrinsic parasitics become critical to nano-CMOS device performance. The thesis describes device capacitance components, analyzes the CMOS inverter, and obtains new insights into the inverter propagation delay in nano-CMOS. The projection of a.c. performance of scaled devices is obtained. The statistical variability of electrical characteristics, due to intrinsic parameter fluctuation sources, in contemporary and scaled decananometer MOSFETs is systematically investigated for the first time. The statistical variability sources: random discrete dopants, gate line edge roughness and poly-silicon granularity are simulated, in combination, in an ensemble of microscopically different devices. An increasing trend in the standard deviation of the threshold voltage as a function of scaling is observed. The introduction of high-k/metal gates improves electrostatic integrity and slows this trend. Statistical evaluations of variability in Ion and Ioff as a function of scaling are also performed. For the first time, the impact of strain on statistical variability is studied. Gate line edge roughness results in areas of local channel shortening, accompanied by locally increased strain, both effects increasing the local current. Variations are observed in both the drive current, and in the drive current enhancement normally expected from the application of strain. In addition, the effects of shallow trench isolation (STI) on MOSFET performance and on its statistical variability are investigated for the first time. The inverse-narrow-width effect of STI enhances the current density adjacent to it. This leads to a local enhancement of the influence of junction shapes adjacent to the STI. There is also a statistical impact on the threshold voltage due to random STI induced traps at the silicon/oxide interface

Monte Carlo study of current variability in UTB SOI DG MOSFETs

The scaling of conventional silicon based MOSFETs is increasingly difficult into the nanometer regime due to short channel effects, tunneling and subthreshold leakage current. Ultra-thin body silicon-on-insulator based architectures offer a promising alternative, alleviating these problems through their geometry. However, the transport behaviour in these devices is more complex, especially for silicon thicknesses below 10 nm, with enhancement from band splitting and volume inversion competing with scattering from phonons, Coulomb interactions, interface roughness and body thickness fluctuation. Here, the effect of the last scattering mechanism on the drive current is examined as it is considered a significant limitation to device performance for body thicknesses below 5 nm. A simulation technique that properly captures non-equilibrium transport, includes quantum effects and maintains computational efficiency is essential for the study of this scattering mechanism. Therefore, a 3D Monte Carlo simulator has been developed which includes this scattering effect in an ab initio fashion, and quantum corrections using the Density Gradient formalism. Monte Carlo simulations using `frozen field' approximation have been carried out to examine the dependence of mobility on silicon thickness in large, self averaging devices. This approximation is then used to carry out statistical studies of uniquely different devices to examine the variability of on-current. Finally, Monte Carlo simulations self consistent with Poisson's equation have been carried out to further investigate this mechanism

Numerical simulation of advanced CMOS and beyond CMOS devices

Co-supervisore: Marco PalaopenLo scaling dei dispositivi elettronici e l'introduzione di nuove opzioni tecnologiche per l'aumento delle prestazioni richiede un costante supporto dal punto di vista della simulazione numerica. Questa tesi si inquadra in tale ambito ed in particolare si prefigge lo scopo di sviluppare due tool software completi basati su tecniche avanzate al fine di predire le prestazioni di dipositivi nano-elettronici progettati per i futuri nodi tecnologiciDottorato di ricerca in Ingegneria industriale e dell'informazioneembargoed_20131103Conzatti, Francesc

Characterisation and noise analysis of high Ge content p-channel SiGe MOSFETs fabricated using virtual substrates

This thesis demonstrates the advantages and disadvantages of investigated p-type SiGe MOSFETs with high Ge content Si1#xGex p-channel grown on Si1#yGey virtual substrate (VS) (x "0'7$0'9, y "0'3$0'5) in comparison with conventional Si devices. The ways to overcome current difficulties in conventional Si technology and mixed SiGe-Si technology are shown. Current-voltage (I-V) and capacitance-voltage (C-V) DC characteristics for p-channel Si/Si1#xGex/Si1#yGey hetero-MOSFETs with high Ge content (x "0'7$0'9, y"0'3$0'5) are reported. Enhancement in the maximum drain current for the p-SiGe devices in comparison with p-Si control is 2.5-3.0 times. DC characteristic simulations of SiGe p-channel MOSFETs were used to improve the accuracy of MOSFET and heterostructure parameters extraction. Calibrated during the simulation theoretical models were used for future design. The effective mobility, the source-drain access resistance, the doping profile, the layers thickness, oxide/semiconductor interface charge and other important characteristics were extracted. The effective mobility values, extracted for p-Si0%3Ge0%7 MOSFETs, exceed the hole mobility in a conventional Si p-MOS device by a factor of 3.5 and reach the mobility of conventional Si n-MOS transistors. The peak value of me f f = 760 cm2V#1s#1 at field 0.08 MVcm#1 was obtained for p-Si/Si0%2Ge0%8/ Si0%5Ge0%5 MOSFETs. Efficiency of special n-type doped layer, also known as "punch-through" stopper, introduced into heterostructure is shown. Perfect I-V and also low frequency noise characteristics of investigated MOSFET show that the p-type Si/Si1#xGex/Si1#yGey (x "0'7 $0'9, x$y "0'3$0'4) heterostructures with "punch-through" stopper could be very impressive opportunity to conventional Si for modern semiconductor industry. For the first time, quantitative explanation of the low frequency noise reduction in metamorphic, high Ge content, SiGe p-MOSFETs compared to Si p-MOSFETs have been proposed. Quantitative analysis demonstrates the importance of both carrier number fluctuations and correlated mobility fluctuations (CMF) components to the 1/ f noise of surface channel Si p-MOSFET, but the absence of CMF for buried channel p-Si0%3Ge0%7 and p- Si0%2Ge0%8 MOSFETs. The low frequency noise was measured to be three times smaller for a 0.55 mm effective gate length p-Si0%3Ge0%7 MOSFET than the Si control, at linear regime (VDS = -50 mV) and high gate overdrive voltage (Vgt= -1.5 V). This result is very important, because we have reduction in LF noise at high gate overdrive voltages, which are typical for analogue and power electronics application. Both DC and low frequency noise characteristics show that access source and drain resistance for metamorphic p-SiGe MOSFETs (RS +RD ,1.5-2.0kW !mm) roughly 2 times lower then for conventional p-Si MOSFETs