Modeling Based on Elman Wavelet Neural Network for Class-D Power Amplifiers

In Class-D Power Amplifiers (CDPAs), the power supply noise can intermodulate with the input signal, manifesting into power-supply induced intermodulation distortion (PS-IMD) and due to the memory effects of the system, there exist asymmetries in the PS-IMDs. In this paper, a new behavioral modeling based on the Elman Wavelet Neural Network (EWNN) is proposed to study the nonlinear distortion of the CDPAs. In EWNN model, the Morlet wavelet functions are employed as the activation function and there is a normalized operation in the hidden layer, the modification of the scale factor and translation factor in the wavelet functions are ignored to avoid the fluctuations of the error curves. When there are 30 neurons in the hidden layer, to achieve the same square sum error (SSE) $\epsilon_{min}=10^{-3}$, EWNN needs 31 iteration steps, while the basic Elman neural network (BENN) model needs 86 steps. The Volterra-Laguerre model has 605 parameters to be estimated but still can't achieve the same magnitude accuracy of EWNN. Simulation results show that the proposed approach of EWNN model has fewer parameters and higher accuracy than the Volterra-Laguerre model and its convergence rate is much faster than the BENN model

Modeling and technique to improve PSRR and PS-IMD in analog PWM class-D amplifiers

Although power-supply noise, qualified by power- supply rejection ratio (PSRR), has been recognized as a potential drawback of Class-D amplifiers (CDAs) compared to linear amplifiers, the mechanisms of PSRR for CDAs are not well established. It is also not well recognized that the power-supply noise can intermodulate with the input signal, manifesting into power-supply induced intermodulation distortion (PS-IMD), and that the PS-IMD can be significantly larger than the output distortion component at supply noise frequency. Furthermore, techniques to improve PSRR and PS-IMD are largely unreported in literature. In this brief, by means of a linear model, the PSRR and PS-IMD of single-feedback and double-feedback CDAs are analyzed and analytical expressions derived. A simple method is proposed to improve PSRR and PS-IMD with very low hardware overheads, and the improvement is ~ 26 dB. Analytical expressions for PSRR and PS-IMD of the improved design are derived and the pertinent parameters thereof are investigated. The model and analyses provide practical insight to the mechanisms of PSRR and PS-IMD, and how various parameters may be varied to meet a given specification.Published versio

Sigma-delta class D audio power amplifier in CMOS technology

Master'sMASTER OF ENGINEERIN

Low Power DC-DC Converters and a Low Quiescent Power High PSRR Class-D Audio Amplifier

High-performance DC-DC voltage converters and high-efficient class-D audio amplifiers are required to extend battery life and reduce cost in portable electronics. This dissertation focuses on new system architectures and design techniques to reduce area and minimize quiescent power while achieving high performance. Experimental results from prototype circuits to verify theory are shown. Firstly, basics on low drop-out (LDO) voltage regulators are provided. Demand for system-on-chip solutions has increased the interest in LDO voltage regulators that do not require a bulky off-chip capacitor to achieve stability, also called capacitor- less LDO (CL-LDO) regulators. Several architectures have been proposed; however, comparing these reported architectures proves difficult, as each has a distinct process technology and specifications. This dissertation compares CL-LDOs in a unified manner. Five CL-LDO regulator topologies were designed, fabricated, and tested under common design conditions. Secondly, fundamentals on DC-DC buck converters are presented and area reduction techniques for the external output filter, power stage, and compensator are proposed. A fully integrated buck converter using standard CMOS technology is presented. The external output filter has been fully-integrated by increasing the switching frequency up to 45 MHz. Moreover, a monolithic single-input dual-output buck converter is proposed. This architecture implements only three switches instead of the four switches used in conventional solutions, thus potentially reducing area in the power stage through proper design of the power switches. Lastly, a monolithic PWM voltage mode buck converter with compact Type-III compensation is proposed. This compensation scheme employs a combination of Gm-RC and Active-RC techniques to reduce the area of the compensator, while maintaining low quiescent power consumption and fast transient response. The proposed compensator reduces area by more than 45% when compared to an equivalent conventional Type-III compensator. Finally, basics on class-D audio amplifiers are presented and a clock-free current controlled class-D audio amplifier using integral sliding mode control is proposed. The proposed amplifier achieves up to 82 dB of power supply rejection ratio and a total harmonic distortion plus noise as low as 0.02%. The IC prototype’s controller consumes 30% less power than those featured in recently published works