Modeling Based on Elman Wavelet Neural Network for Class-D Power Amplifiers

In Class-D Power Amplifiers (CDPAs), the power supply noise can intermodulate with the input signal, manifesting into power-supply induced intermodulation distortion (PS-IMD) and due to the memory effects of the system, there exist asymmetries in the PS-IMDs. In this paper, a new behavioral modeling based on the Elman Wavelet Neural Network (EWNN) is proposed to study the nonlinear distortion of the CDPAs. In EWNN model, the Morlet wavelet functions are employed as the activation function and there is a normalized operation in the hidden layer, the modification of the scale factor and translation factor in the wavelet functions are ignored to avoid the fluctuations of the error curves. When there are 30 neurons in the hidden layer, to achieve the same square sum error (SSE) $\epsilon_{min}=10^{-3}$, EWNN needs 31 iteration steps, while the basic Elman neural network (BENN) model needs 86 steps. The Volterra-Laguerre model has 605 parameters to be estimated but still can't achieve the same magnitude accuracy of EWNN. Simulation results show that the proposed approach of EWNN model has fewer parameters and higher accuracy than the Volterra-Laguerre model and its convergence rate is much faster than the BENN model

Low Power High Efficiency Integrated Class-D Amplifier Circuits for Mobile Devices

The consumer’s demand for state-of-the-art multimedia devices such as smart phones and tablet computers has forced manufacturers to provide more system features to compete for a larger portion of the market share. The added features increase the power consumption and heat dissipation of integrated circuits, depleting the battery charge faster. Therefore, low-power high-efficiency circuits, such as the class-D audio amplifier, are needed to reduce heat dissipation and extend battery life in mobile devices. This dissertation focuses on new design techniques to create high performance class-D audio amplifiers that have low power consumption and occupy less space. The first part of this dissertation introduces the research motivation and fundamentals of audio amplification. The loudspeaker’s operation and main audio performance metrics are examined to explain the limitations in the amplification process. Moreover, the operating principle and design procedure of the main class-D amplifier architectures are reviewed to provide the performance tradeoffs involved. The second part of this dissertation presents two new circuit designs to improve the audio performance, power consumption, and efficiency of standard class-D audio amplifiers. The first work proposes a feed-forward power-supply noise cancellation technique for single-ended class-D amplifier architectures to improve the power-supply rejection ratio across the entire audio frequency range. The design methodology, implementation, and tradeoffs of the proposed technique are clearly delineated to demonstrate its simplicity and effectiveness. The second work introduces a new class-D output stage design for piezoelectric speakers. The proposed design uses stacked-cascode thick-oxide CMOS transistors at the output stage that makes possible to handle high voltages in a low voltage standard CMOS technology. The design tradeoffs in efficiency, linearity, and electromagnetic interference are discussed. Finally, the open problems in audio amplification for mobile devices are discussed to delineate the possible future work to improve the performance of class-D amplifiers. For all the presented works, proof-of-concept prototypes are fabricated, and the measured results are used to verify the correct operation of the proposed solutions

Low Power DC-DC Converters and a Low Quiescent Power High PSRR Class-D Audio Amplifier

High-performance DC-DC voltage converters and high-efficient class-D audio amplifiers are required to extend battery life and reduce cost in portable electronics. This dissertation focuses on new system architectures and design techniques to reduce area and minimize quiescent power while achieving high performance. Experimental results from prototype circuits to verify theory are shown. Firstly, basics on low drop-out (LDO) voltage regulators are provided. Demand for system-on-chip solutions has increased the interest in LDO voltage regulators that do not require a bulky off-chip capacitor to achieve stability, also called capacitor- less LDO (CL-LDO) regulators. Several architectures have been proposed; however, comparing these reported architectures proves difficult, as each has a distinct process technology and specifications. This dissertation compares CL-LDOs in a unified manner. Five CL-LDO regulator topologies were designed, fabricated, and tested under common design conditions. Secondly, fundamentals on DC-DC buck converters are presented and area reduction techniques for the external output filter, power stage, and compensator are proposed. A fully integrated buck converter using standard CMOS technology is presented. The external output filter has been fully-integrated by increasing the switching frequency up to 45 MHz. Moreover, a monolithic single-input dual-output buck converter is proposed. This architecture implements only three switches instead of the four switches used in conventional solutions, thus potentially reducing area in the power stage through proper design of the power switches. Lastly, a monolithic PWM voltage mode buck converter with compact Type-III compensation is proposed. This compensation scheme employs a combination of Gm-RC and Active-RC techniques to reduce the area of the compensator, while maintaining low quiescent power consumption and fast transient response. The proposed compensator reduces area by more than 45% when compared to an equivalent conventional Type-III compensator. Finally, basics on class-D audio amplifiers are presented and a clock-free current controlled class-D audio amplifier using integral sliding mode control is proposed. The proposed amplifier achieves up to 82 dB of power supply rejection ratio and a total harmonic distortion plus noise as low as 0.02%. The IC prototype’s controller consumes 30% less power than those featured in recently published works

Design and Implementation of Switching Voltage Integrated Circuits Based on Sliding Mode Control

The need for high performance circuits in systems with low-voltage and low-power requirements has exponentially increased during the few last years due to the sophistication and miniaturization of electronic components. Most of these circuits are required to have a very good efficiency behavior in order to extend the battery life of the device. This dissertation addresses two important topics concerning very high efficiency circuits with very high performance specifications. The first topic is the design and implementation of class D audio power amplifiers, keeping their inherent high efficiency characteristic while improving their linearity performance, reducing their quiescent power consumption, and minimizing the silicon area. The second topic is the design and implementation of switching voltage regulators and their controllers, to provide a low-cost, compact, high efficient and reliable power conversion for integrated circuits. The first part of this dissertation includes a short, although deep, analysis on class D amplifiers, their history, principles of operation, architectures, performance metrics, practical design considerations, and their present and future market distribution. Moreover, the harmonic distortion of open-loop class D amplifiers based on pulse-width modulation (PWM) is analyzed by applying the duty cycle variation technique for the most popular carrier waveforms giving an easy and practical analytic method to evaluate the class D amplifier distortion and determine its specifications for a given linearity requirement. Additionally, three class D amplifiers, with an architecture based on sliding mode control, are proposed, designed, fabricated and tested. The amplifiers make use of a hysteretic controller to avoid the need of complex overhead circuitry typically needed in other architectures to compensate non-idealities of practical implementations. The design of the amplifiers based on this technique is compact, small, reliable, and provides a performance comparable to the state-of-the-art class D amplifiers, but consumes only one tenth of quiescent power. This characteristic gives to the proposed amplifiers an advantage for applications with minimal power consumption and very high performance requirements. The second part of this dissertation presents the design, implementation, and testing of switching voltage regulators. It starts with a description and brief analysis on the power converters architectures. It outlines the advantages and drawbacks of the main topologies, discusses practical design considerations, and compares their current and future market distribution. Then, two different buck converters are proposed to overcome the most critical issue in switching voltage regulators: to provide a stable voltage supply for electronic devices, with good regulation voltage, high efficiency performance, and, most important, a minimum number of components. The first buck converter, which has been designed, fabricated and tested, is an integrated dual-output voltage regulator based on sliding mode control that provides a power efficiency comparable to the conventional solutions, but potentially saves silicon area and input filter components. The design is based on the idea of stacking traditional buck converters to provide multiple output voltages with the minimum number of switches. Finally, a fully integrated buck converter based on sliding mode control is proposed. The architecture integrates the external passive components to deliver a complete monolithic solution with minimal silicon area. The buck converter employs a poly-phase structure to minimize the output current ripple and a hysteretic controller to avoid the generation of an additional high frequency carrier waveform needed in conventional solutions. The simulated results are comparable to the state-of-the-art works even with no additional post-fabrication process to improve the converter performance

Sigma-delta class D audio power amplifier in CMOS technology

Master'sMASTER OF ENGINEERIN

High Frequency DC/DC Boost Converter

The goal of this work was to design and test a functional proof of concept of a high frequency DC to DC boost converter. The scope of this work included the design, simulation, part selection, PCB layout, fabrication, and testing of the three major design blocks. The design uses a closed loop error amplifier circuit, a power stage, and a ramp waveform generator circuit. The switching frequency will be adjustable, with a maximum goal of 20MHz

Modélisation en vue de l'intégration d'un système audio de micro puissance comprenant un haut-parleur MEMS et son amplificateur

Ce manuscrit de thèse propose l'optimisation de l'ensemble de la chaîne de reproduction sonore dans un système embarqué. Le premier axe de recherche introduit les notions générales concernant les systèmes audio embarqués nécessaires à la bonne compréhension du contexte de la recherche. Le principe de conversion de l'ensemble de la chaine est présenté afin de comprendre les différentes étapes qui composent un système audio. Un état de l'art présente les différents types de haut-parleurs ainsi que l'électronique associé les plus couramment utilisées dans les systèmes embarqués. Le second axe de recherche propose une approche globale : une modélisation électrique du haut-parleur (tenant compte d'un nombre optimal de paramètres) permet à un électronicien de mieux appréhender les phénomènes non-linéaires du haut-parleur qui dégradent majoritairement la qualité audio. Il en résulte un modèle viable qui permet d'évaluer la non-linéarité intrinsèque du haut-parleur et d'en connaitre sa cause. Les résultats des simulations montrent que le taux de distorsion harmonique intrinsèque au haut-parleur est supérieur à celui généré par un amplificateur. Le troisième axe de recherche met en avant l'impact du contrôle du transducteur. L'objectif étant de savoir s'il existe une différence, du point de vue de la qualité audio, entre la commande asservie par une tension ou par un courant, d'un micro-haut-parleur électrodynamique. Pour ce type de transducteur et à ce niveau de la modélisation, le contrôle en tension est équivalent à contrôler directement le haut-parleur en courant. Néanmoins, une solution alternative (ne dégradant pas davantage la qualité audio du signal) pourrait être de contrôler le micro-haut-parleur en courant. Le quatrième axe de recherche propose d'adapter les spécifications des amplificateurs audio aux performances des micro-haut-parleurs. Une étude globale (énergétique) démontre qu'un des facteurs clés pour améliorer l'efficacité énergétique du côté de l'amplificateur audio est la minimalisation de la consommation statique en courant, en maximalisant le rendement à puissance nominale. Pour les autres spécifications, l'approche globale se base sur l'étude de l'impact de la spécification d'un amplificateur sur la partie acoustique. Cela nous a par exemple permis de réduire la contrainte en bruit de 300%. Le dernier axe de recherche s'articule autour d'un nouveau type de transducteur : un micro-haut-parleur en technologie MEMS. La caractérisation électroacoustique présente l'amélioration en terme de qualité audio (moins de 0,016% de taux de distorsion harmonique) et de plage de fréquence utile allant de 200 Hz à 20 kHz le tout pour un niveau sonore moyen de 80dB (10cm). La combinaison de tous les efforts présente un réel saut technologique. Enfin, la démarche globale d'optimisation de la partie électrique a été appliquée aux performances du MEMS dans la dernière section, ce qui a notamment permis de réduire la contrainte en bruit de 500%.This thesis proposes the optimization of the whole sound reproduction chain in an embedded system. The first research axis is introduces the general concepts concerning audio systems necessary for the good understanding of the context of research. The principle of conversion of the entire chain is presented to understand the stages that make up a sound system. A state of the art presents various loudspeakers and the associated electronics most commonly used in embedded systems. The second research axis proposes a global approach: electric modeling of loudspeaker (taking into account an optimum number of parameters) that allows electronics engineer a better understanding of the nonlinear phenomena that degrade mostly audio quality in loudspeakers. It results in a sustainable model which evaluates the intrinsic non-linearity in loudspeakers and to know its cause. The simulation results show that the total harmonic distortion intrinsic to the loudspeaker is higher than that the distortion generated by an amplifier. The third research axis highlights the impact of the control of the transducer. The aim is to find out if there is a difference, in terms of audio quality, between the feedback control by voltage or current, for an electrodynamic micro-speaker. For this type of transducer and at this level of modeling, voltage control is equivalent to directly control the current of the micro-speaker. However, an alternative solution (not further degrading the signal audio quality) could be to control directly the micro-speaker by a current. The fourth research axis proposes to adapt the audio amplifiers specification to the performance of the micro-speakers. A comprehensive study of an energy point of view shows that a key factor for improving the energy efficiency of the audio amplifier is the minimization of the static power consumption and the maximization of the performance at nominal power. For other specifications, the global approach is based on the study of the impact of the specification of an amplifier on the sound pressure level. This has allowed, for example to reduce the stress in output noise voltage by a ratio of 300 %. The last research axis focuses on a new type of transducer: a micro-speaker in MEMS technology. Electroacoustic characterization shows the improvement: in terms of audio quality (less than 0.016 % total harmonic distortion) and the useful frequency range from 200 Hz to 20 kHz, the whole for an average sound level of 80 dB (10 cm). The combination of all the efforts presents a real technological leap. Finally, the overall process of optimization of the electrical part has been applied to the performance of MEMS in this last section, which has resulted, for example, in a reduction in the noise constraint of 500 %.VILLEURBANNE-DOC'INSA-Bib. elec. (692669901) / SudocSudocFranceF

High Performance RF and Basdband Analog-to-Digital Interface for Multi-standard/Wideband Applications

The prevalence of wireless standards and the introduction of dynamic standards/applications, such as software-defined radio, necessitate the next generation wireless devices that integrate multiple standards in a single chip-set to support a variety of services. To reduce the cost and area of such multi-standard handheld devices, reconfigurability is desirable, and the hardware should be shared/reused as much as possible. This research proposes several novel circuit topologies that can meet various specifications with minimum cost, which are suited for multi-standard applications. This doctoral study has two separate contributions: 1. The low noise amplifier (LNA) for the RF front-end; and 2. The analog-to-digital converter (ADC). The first part of this dissertation focuses on LNA noise reduction and linearization techniques where two novel LNAs are designed, taped out, and measured. The first LNA, implemented in TSMC (Taiwan Semiconductor Manufacturing Company) 0.35Cm CMOS (Complementary metal-oxide-semiconductor) process, strategically combined an inductor connected at the gate of the cascode transistor and the capacitive cross-coupling to reduce the noise and nonlinearity contributions of the cascode transistors. The proposed technique reduces LNA NF by 0.35 dB at 2.2 GHz and increases its IIP3 and voltage gain by 2.35 dBm and 2dB respectively, without a compromise on power consumption. The second LNA, implemented in UMC (United Microelectronics Corporation) 0.13Cm CMOS process, features a practical linearization technique for high-frequency wideband applications using an active nonlinear resistor, which obtains a robust linearity improvement over process and temperature variations. The proposed linearization method is experimentally demonstrated to improve the IIP3 by 3.5 to 9 dB over a 2.5–10 GHz frequency range. A comparison of measurement results with the prior published state-of-art Ultra-Wideband (UWB) LNAs shows that the proposed linearized UWB LNA achieves excellent linearity with much less power than previously published works. The second part of this dissertation developed a reconfigurable ADC for multistandard receiver and video processors. Typical ADCs are power optimized for only one operating speed, while a reconfigurable ADC can scale its power at different speeds, enabling minimal power consumption over a broad range of sampling rates. A novel ADC architecture is proposed for programming the sampling rate with constant biasing current and single clock. The ADC was designed and fabricated using UMC 90nm CMOS process and featured good power scalability and simplified system design. The programmable speed range covers all the video formats and most of the wireless communication standards, while achieving comparable Figure-of-Merit with customized ADCs at each performance node. Since bias current is kept constant, the reconfigurable ADC is more robust and reliable than the previous published works

Modeling and technique to improve PSRR and PS-IMD in analog PWM class-D amplifiers

Although power-supply noise, qualified by power- supply rejection ratio (PSRR), has been recognized as a potential drawback of Class-D amplifiers (CDAs) compared to linear amplifiers, the mechanisms of PSRR for CDAs are not well established. It is also not well recognized that the power-supply noise can intermodulate with the input signal, manifesting into power-supply induced intermodulation distortion (PS-IMD), and that the PS-IMD can be significantly larger than the output distortion component at supply noise frequency. Furthermore, techniques to improve PSRR and PS-IMD are largely unreported in literature. In this brief, by means of a linear model, the PSRR and PS-IMD of single-feedback and double-feedback CDAs are analyzed and analytical expressions derived. A simple method is proposed to improve PSRR and PS-IMD with very low hardware overheads, and the improvement is ~ 26 dB. Analytical expressions for PSRR and PS-IMD of the improved design are derived and the pertinent parameters thereof are investigated. The model and analyses provide practical insight to the mechanisms of PSRR and PS-IMD, and how various parameters may be varied to meet a given specification.Published versio