Determining layer number of two dimensional flakes of transition-metal dichalcogenides by the Raman intensity from substrate

Transition-metal dichalcogenide (TMD) semiconductors have been widely studied due to their distinctive electronic and optical properties. The property of TMD flakes is a function of its thickness, or layer number (N). How to determine N of ultrathin TMDs materials is of primary importance for fundamental study and practical applications. Raman mode intensity from substrates has been used to identify N of intrinsic and defective multilayer graphenes up to N=100. However, such analysis is not applicable for ultrathin TMD flakes due to the lack of a unified complex refractive index ($\tilde{n}$) from monolayer to bulk TMDs. Here, we discuss the N identification of TMD flakes on the SiO$_2$/Si substrate by the intensity ratio between the Si peak from 100-nm (or 89-nm) SiO$_2$/Si substrates underneath TMD flakes and that from bare SiO$_2$/Si substrates. We assume the real part of $\tilde{n}$ of TMD flakes as that of monolayer TMD and treat the imaginary part of $\tilde{n}$ as a fitting parameter to fit the experimental intensity ratio. An empirical $\tilde{n}$, namely, $\tilde{n}_{eff}$, of ultrathin MoS$_{2}$, WS$_{2}$ and WSe$_{2}$ flakes from monolayer to multilayer is obtained for typical laser excitations (2.54 eV, 2.34 eV, or 2.09 eV). The fitted $\tilde{n}_{eff}$ of MoS$_{2}$ has been used to identify N of MoS$_{2}$ flakes deposited on 302-nm SiO$_2$/Si substrate, which agrees well with that determined from their shear and layer-breathing modes. This technique by measuring Raman intensity from the substrate can be extended to identify N of ultrathin 2D flakes with N-dependent $\tilde{n}$ . For the application purpose, the intensity ratio excited by specific laser excitations has been provided for MoS$_{2}$, WS$_{2}$ and WSe$_{2}$ flakes and multilayer graphene flakes deposited on Si substrates covered by 80-110 nm or 280-310 nm SiO$_2$ layer.Comment: 10 pages, 4 figures. Accepted by Nanotechnolog

Fundamental limitations in microelectronics — I. MOS technology

The physical phenomena which will ultimately limit MOS circuit miniaturization are considered. It is found that the minimum MOS transistor size is determined by gate oxide breakdown and drain-source punch-through. Other factors which limit device size are drain-substrate breakdown, drain ‘corner’ breakdown and substrate doping fluctuations. However these limitations are less severe than the oxide breakdown limitation mentioned above. Power dissipation and metal migration limit the frequency and/or packing density of fully dynamic and of complementary MOS circuits. In static non-complementary circuits, power dissipation is the principal limitation of the number of circuit functions per chip. The channel length of a minimum size MOS transistor is a factor of 10 smaller than that of the smallest present day devices. The tolerances required to manufacture such a transistor are compatible with electron beam masking techniques. It is thus possible to envision fully dynamic silicon chips with up to 10^7–10^8 MOS transistors per cm^2

Dry transfer of CVD graphene using MoS2_2-based stamps

Recently, a contamination-free dry transfer method for graphene grown by chemical vapor deposition (CVD) has been reported that allows to directly pick-up graphene from the copper growth substrate using a flake of hexagonal boron nitride (hBN), resulting in ultrahigh charge carrier mobility and low overall doping. Here, we report that not only hBN, but also flakes of molybdenum disulfide (MoS$_2$) can be used to dry transfer graphene. This, on one hand, allows for the fabrication of complex van-der-Waals heterostructures using CVD graphene combined with different two-dimensional materials and, on the other hand, can be a route towards a scalable dry transfer of CVD graphene. The resulting heterostructures are studied using low temperature transport measurements revealing a strong charge carrier density dependence of the carrier mobilities (up to values of 12,000 cm$^2$/(Vs)) and the residual charge carrier density fluctuations near the charge neutrality point when changing the carrier density in the MoS$_2$ by applying a top gate voltage.Comment: 5 pages, 3 figure

General theoretical description of angle-resolved photoemission spectroscopy of van der Waals structures

We develop a general theory to model the angle-resolved photoemission spectroscopy (ARPES) of commensurate and incommensurate van der Waals (vdW) structures, formed by lattice mismatched and/or misaligned stacked layers of two-dimensional materials. The present theory is based on a tight-binding description of the structure and the concept of generalized umklapp processes, going beyond previous descriptions of ARPES in incommensurate vdW structures, which are based on continuous, low-energy models, being limited to structures with small lattice mismatch/misalignment. As applications of the general formalism, we study the ARPES bands and constant energy maps for two structures: twisted bilayer graphene and twisted bilayer MoS$_{2}$. The present theory should be useful in correctly interpreting experimental results of ARPES of vdW structures and other systems displaying competition between different periodicities, such as two-dimensional materials weakly coupled to a substrate and materials with density wave phases.Comment: 17 pages, 7 figure

A Radiation hard bandgap reference circuit in a standard 0.13um CMOS Technology

With ongoing CMOS evolution, the gate-oxide thickness steadily decreases, resulting in an increased radiation tolerance of MOS transistors. Combined with special layout techniques, this yields circuits with a high inherent robustness against X-rays and other ionizing radiation. In bandgap voltage references, the dominant radiation-susceptibility is then no longer associated with the MOS transistors, but is dominated by the diodes. This paper gives an analysis of radiation effects in both MOSdevices and diodes and presents a solution to realize a radiation-hard voltage reference circuit in a standard CMOS technology. A demonstrator circuit was implemented in a standard 0.13 m CMOS technology. Measurements show correct operation with supply voltages in the range from 1.4 V down to 0.85 V, a reference voltage of 405 mV 7.5 mV ( = 6mVchip-to-chip statistical spread), and a reference voltage shift of only 1.5 mV (around 0.8%) under irradiation up to 44 Mrad (Si)

Synthesis of Cerium Dioxide High-k Thin Films as a Gate Dielectric in MOS Capacitor

In the present study, the Al/CeO2 / p-Si MOS capacitor was fabricated by depositing the Aluminium (Al) metal layer by thermal evaporation technique on sol-gel derived CeO2 high-k thin films on p-Si substrate. The deposited CeO2 films were characterized by Ellipsometer to study the refractive index that is determined to be 3.62. The FTIR analysis was carried out to obtain chemical bonding characteristics. Capacitance-voltage measurements of Al/CeO2 /p-Si MOS capacitor were carried out to determine the dielectric constant, equivalent oxide thickness (EOT) and flat band shift (VFB) for the deposited CeO2 film of 16.22, 1.62 nm and 0.7 V respectively. The conductance voltage curve was used to determine the interface trap density (Dit) at the CeO2 / p-Si interface that is calculated to be 1.29 × 1013 cm – 2 eV – 1 for measurement frequency of 500 kHz. When you are citing the document, use the following link http://essuir.sumdu.edu.ua/handle/123456789/3192

Selective Passivation of GeO2/Ge Interface Defects in Atomic Layer Deposited High-k MOS Structures.

Effective passivation of interface defects in high-k metal oxide/Ge gate stacks is a longstanding goal of research on germanium metal-oxide-semiconductor devices. In this paper, we use photoelectron spectroscopy to probe the formation of a GeO2 interface layer between an atomic layer deposited Al2O3 gate dielectric and a Ge(100) substrate during forming gas anneal (FGA). Capacitance- and conductance-voltage data were used to extract the interface trap density energy distribution. These results show selective passivation of interface traps with energies in the top half of the Ge band gap under annealing conditions that produce GeO2 interface layer growth. First-principles modeling of Ge/GeO2 and Ge/GeO/GeO2 structures and calculations of the resulting partial density of states (PDOS) are in good agreement with the experiment results