Mixed Static/dynamic Profiling For Dictionary Based Code Compression

Many compression techniques have been proposed to accommodate ever increasing software pieces into restricted memory area in embedded systems. Recently, these techniques have been shown to improve other important design constrains like energy and performance. This paper proposes a blended dictionary model based on static/dynamic profiling that lead to best trade-offs on compression, performance and energy savings. We also propose a new dictionary based code compression algorithm, independent of the cache organization and processor, to support our experiments. A mix of benchmarks from Mediabench and MiBench suites revels that compression ratios of 75% can be obtained while decreasing bus accesses to the cache by 31% for the Leon processor. These results approach simultaneously the best solutions of when using pure static or pure dynamic information based dictionaries techniques. ©2003 IEEE.159163Wolfe, A., Chainin, A., Executing compressed programs on an embedded RISC architecture (1992) Proc. of Int'l Symp. on Microarchitecture, pp. 81-91. , DecBenini, L., Macci, A., Nannarelli, A., Cached-code compression for energy minimization in embedded processor (2001) Proc. of ISPLED'01, pp. 322-327. , AugLekatsas, H., Henkel, J., Wolf, W., Design and simulation of a pipelined decompression architecture for embedded systems (2001) Proc. of ISSS'01., pp. 63-68. , OctDebray, S., Evans, W., Profile-guided code compression (2002) Proc. of the ACM SIGPLAN on Programming Language Design and Implementation., pp. 95-105. , JunXie, Y., Wolf, W., Lekatsas, H., Profile-driven selective code compression (2003) Proc. of DATE'03, pp. 462-467. , MarLekatsas, H., Henkel, J., Jakkula, V., Design of one-cycle decompression hardware for performance increase in embedded systems (2002) Proc. of DAC'02, pp. 34-39. , Jun(2003) Leon [Online], , http://www.gaisler.com, May AvailableHill, M.D., (2003) DineroIV Trace-driven Simulator, , http://www.cs.wisc.edu/~markhill/DineroIV, May [Online]. AvailableGuthaus, M., Ringenberg, J., Ernst, D., Austin, T., Mudge, T., Brown, R., MiBench: A free, commercially representative embedded benchmark suite IEEE 4th Annual Workshop on Workload Characterization. Dec 2001Lee, C., Potkonjak, M., Mangione-Smith, W., Mediabench: A tool for evaluating and synthesizing multimedia and communication system (1997) IEEE MICRO-30, pp. 330-337. , De

Design Of A Decompressor Engine On A Sparc Processor

Code compression, initially conceived as an effective technique to reduce code size in embedded systems, today also brings advantages in terms of performance and energy consumption, due to an increase in the cache hit ratio. This paper proposes the design of a code decompressor engine for our dictionary-based method, embedding it into the Leon (SPARC V8) processor. Our design guarantees that the processor cycle-time is maintained and the decompression is performed on-the-fly. We have achieved a functional implementation on a FPGA1 with compression ratios ranging from 72% to 88%, performance improvement as high as 45% and a reduction on energy consumption reaching 35%, validated through two real-world benchmarks suites: MediaBench and MiBench. We also explore some trade-offs between compression ratio and performance. Copyright 2005 ACM.110114Benini, L., Macii, A., Nannarelli, A., Code compression for cache energy minimization in embedded systems (2002) IEE Proceedings on Computers and Digital Techniques, 149 (4), pp. 157-163. , JulyGaisler, J., Leon2 processor user's manual 1.0.24 (2004), SeptLEON-PCI-XC2V Development Board (2004) User Manual, 6. , Gaisler ResearchGuthaus, M., Ringenberg, J., Ernst, D., Austin, T., Mudge, T., Mibench: A free, commercially representative embedded benchmark suite (2001) Proc. of the IEEE 4th Annual Workshop on Workload Characterization, pp. 3-14. , DecLee, C., Potkonjak, M., Mangione-Smith, W., Mediabench: A tool for evaluating and synthesizing multimedia communication systems (1997) Proc. Int 'I Symp. on Microarchitecture, pp. 330-337. , DecLekatsas, H., Henkel, J., Wolf, W., Code compression for low power embedded system design (2000) Proc. ACM/IEEE Design Automation Conference, pp. 294-299Lekatsas, H., Henkel, J., Wolf, W., Design and simulation of a pipelined decompression architecture for embedded systems (2001) Proc. ACM/IEEE Int'l Symp. on System Synthesis, pp. 63-68. , OctNetto, E.W., Azevedo, R., Centoducatte, P., Araujo, G., Mixed static/dynamic profiling for dictionary based code compression (2003) Proc. of the International Symposium on System-on-Chip, pp. 159-163. , NovNetto, E.W., Azevedo, R., Centoducatte, P., Araujo, G., Multi-profile based code compression (2004) Proc. ACM/IEEE Design Automation Conference, , JuneWolfe, A., Chanin, A., Executing compressed programs on an embedded RISC architecture (1992) Proc. Int'l Symp. on Microarchitecture, pp. 81-91. , No

Exploiting The Area X Performance Trade-off With Code Compression

Code compression has been shown to be efficient in code size reduction and, recently in performance improvement. In this paper we use a compression method, the ComPacket, which has a very fast decompressor in hardware, to compress selective regions of the code (the inner-loops) to improve performance and in the complementary regions we use the Instruction Based Compression (IBC) method to sustain the code size reduction both at the same time. Using the Ieon (SPARC v8) platform and benchmarks from Mediabench and MiBench suites we reached 29% of memory area reduction, on average, and a speed-up of 1.8 simultaneously. © 2005 IEEE.20054245Wolfe, A., Chanin, A., Executing Compressed Programs on an Embedded RISC Architecture (1992) Proc. of ACM/IEEE Annual International Symposium on Microarchitecture, pp. 81-91. , NovAraujo, G., Centoducatte, P., Azevedo, R., Pannain, R., Expression tree based algorithms for code compression on embedded RISC architectures (2000) IEEE Transactions on VLSI Systems, 8 (5), pp. 530-533. , OctWanderley Netto, E., Azevedo, R., Centoducatte, P., Araujo, G., (2003) Mixed Static/Dynamic Profiling for Dictionary Based Code Compression, pp. 159-163. , SoC, NovBenini, L., Macci, A., Nannarelli, A., Cached-code compression for energy minimization in embedded processor (2001) Proc. of ISPLED'01, pp. 322-327. , AugLekatsas, H., Henkel, J., Jakkula, V., Design of one-cycle decompression hardware for performance increase in embedded systems (2002) Proc. of DAC'02, pp. 34-39. , JunKemp, T., Montoye, R., Auerbach, D., Harper, J., Palmer, J., A Decompression Core for PowerPC (1998) IBM Journal of Research and Development, 42 (6), pp. 807-812. , SepKirovski, D., Kin, J., Mangione-Smith, W., Procedure Based Program Compression (1997) Proc. of ACM/IEEE Annual International Symposium on Microarchitecture, pp. 194-203. , DecGaisler, G., Leon, (2003), http://www.gaisler.com, OnLine, Oct, AvailableLee, C., Potkonjak, M., Mangione-Smith, W., Mediabench: A tool for evaluating and synthesizing multimedia communication systems (1997) Proc. of ACM/IEEE Annual International Symposium on Microarchitecture, pp. 330-337. , DecGuthaus, M., Ringenberg, J., Ernst, D., Austin, T., Mudge, T., Mibench: A free, commercially representative mbedded benchmark suite (2001) Proc. of the IEEE 4th Annual Workshop on Workload Characterization, pp. 3-14. , De

Multi-profile Based Code Compression

Code compression has been shown to be an effective technique to reduce code size in memory constrained embedded systems. It has also been used as a way to increase cache hit ratio, thus reducing power consumption and improving performance. This paper proposes an approach to mix static/dynamic instruction profiling in dictionary construction, so as to best exploit trade-offs in compression ratio/performance. Compressed instructions are stored as variable-size indices into fixed-size codewords, eliminating compressed code misalignments. Experimental results, using the Leon (SPARCv8) processor and a program mix from MiBench and Mediabench, show that our approach halves the number of cache accesses and power consumption while produces compression ratios as low as 56%.244249Araujo, G., Centoducatte, P., Azevedo, R., Pannain, R., Expression tree based algorithms for code compression on embedded RISC architectures (2000) IEEE Transactions on VLSI Systems, 8 (5), pp. 530-533. , OctBenini, L., Macci, A., Nannarelli, A., Cached-code compression for energy minimization in embedded processor (2001) Proceedings of the International Symposium on Low Power Electronics and Design, pp. 322-327. , AugDebray, S., Evans, W., Profile-guided code compression (1998) Proceedings of the SIGPLAN Conference on Programming Language Design and Implementation, pp. 95-105. , JuneGaisler, G.L., (2003), www.gaisler.comGuthaus, M., Ringenberg, M., Ernst, D., Austin, T., Mudge, T., Brown, R., MiBench: A free, commercially representative embedded benchmark suite (2001) Proceedings of the IEEE 4th Annual Workshop on Workload Characterization, pp. 3-14. , DecHennessy, J., Patterson, D., (2002) Computer Architecture: A Quantitative Approach, 3rd Ed., , Morgan Kaufmann Publ(1998) CodePack: PowerPC Code Compression Utility User's Manual. V3., , IBM CorporationLee, C., Potkonjak, M., Mangione-Smith, W., MediaBench: A tool for evaluating and synthesizing multimedia communication system (1997) Proceedings of the Int'l Symp. on Microarchitecture, pp. 330-337. , DecLefurgy, C., Bird, P., Chen, I.-C., Mudge, T., Improving code density using compression technique (1997) Proc. of the Int'l Symp. on Microarchitecture, pp. 194-203. , DecLekatsas, H., Henkel, J., Jakkula, V., Design of one-cycle decompression hardware for performance increase in embedded systems (2002) Proceedings of the Design Automation Conference, pp. 34-39. , JuneLekatsas, H., Wolf, W., SAMC: A code compression algorithm for embedded systems (1999) IEEE Transactions on CAD, 18 (12), pp. 1689-1701. , DecSeal, D., ARM Architecture Reference Manual, 2nd Ed., , Adison-Wesley, Reading/MA, 2000Wanderley Netto, E., Azevedo, R., Centoducatte, P., Araujo, G., Mixed static/dynamic profiling for dictionary based code compression (2003) Proceedings of the International Symposium on System-on-chip, pp. 159-163. , NovWilton, S., Jouppi, N., CACTI: An enhanced cache access and cycle time model (1996) IEEE J. of Solid-state Circuits, 35 (5), pp. 677-688. , MayWolfe, A., Chanin, A., Executing compressed programs on an embedded RISC architecture (1992) Proceedings of the Int'l Symp. on Microarchitecture, pp. 81-91. , De