An algorithm for the synthesis of NAND logic networks using a diagrammatic approach

A diagrammatic approach is presented for the synthesis of multilevel NAND networks realizing combinational logic expressions. The network synthesized is restricted to only uncomplemented inputs. The synthesis algorithm involves the determination of minimum sum of products and product of sums expressions for a Boolean function, construction of an α-ß diagram from these expressions followed by implementation with NAND gates directly from the diagram. The resulting network is a minimal or near minimal NAND gate realization of the given function. The algorithm is applicable to completely or incompletely specified Boolean functions and is extended to include NOR synthesis --Abstract, page 2

Geometrical organization of solutions to random linear Boolean equations

The random XORSAT problem deals with large random linear systems of Boolean variables. The difficulty of such problems is controlled by the ratio of number of equations to number of variables. It is known that in some range of values of this parameter, the space of solutions breaks into many disconnected clusters. Here we study precisely the corresponding geometrical organization. In particular, the distribution of distances between these clusters is computed by the cavity method. This allows to study the `x-satisfiability' threshold, the critical density of equations where there exist two solutions at a given distance.Comment: 20 page

Introduction to Logic Circuits & Logic Design with VHDL

The overall goal of this book is to fill a void that has appeared in the instruction of digital circuits over the past decade due to the rapid abstraction of system design. Up until the mid-1980s, digital circuits were designed using classical techniques. Classical techniques relied heavily on manual design practices for the synthesis, minimization, and interfacing of digital systems. Corresponding to this design style, academic textbooks were developed that taught classical digital design techniques. Around 1990, large-scale digital systems began being designed using hardware description languages (HDL) and automated synthesis tools. Broad-scale adoption of this modern design approach spread through the industry during this decade. Around 2000, hardware description languages and the modern digital design approach began to be taught in universities, mainly at the senior and graduate level. There were a variety of reasons that the modern digital design approach did not penetrate the lower levels of academia during this time. First, the design and simulation tools were difficult to use and overwhelmed freshman and sophomore students. Second, the ability to implement the designs in a laboratory setting was infeasible. The modern design tools at the time were targeted at custom integrated circuits, which are cost- and time-prohibitive to implement in a university setting. Between 2000 and 2005, rapid advances in programmable logic and design tools allowed the modern digital design approach to be implemented in a university setting, even in lower-level courses. This allowed students to learn the modern design approach based on HDLs and prototype their designs in real hardware, mainly field programmable gate arrays (FPGAs). This spurred an abundance of textbooks to be authored teaching hardware description languages and higher levels of design abstraction. This trend has continued until today. While abstraction is a critical tool for engineering design, the rapid movement toward teaching only the modern digital design techniques has left a void for freshman- and sophomore-level courses in digital circuitry. Legacy textbooks that teach the classical design approach are outdated and do not contain sufficient coverage of HDLs to prepare the students for follow-on classes. Newer textbooks that teach the modern digital design approach move immediately into high-level behavioral modeling with minimal or no coverage of the underlying hardware used to implement the systems. As a result, students are not being provided the resources to understand the fundamental hardware theory that lies beneath the modern abstraction such as interfacing, gate-level implementation, and technology optimization. Students moving too rapidly into high levels of abstraction have little understanding of what is going on when they click the “compile and synthesize” button of their design tool. This leads to graduates who can model a breadth of different systems in an HDL but have no depth into how the system is implemented in hardware. This becomes problematic when an issue arises in a real design and there is no foundational knowledge for the students to fall back on in order to debug the problem

On the construction of model Hamiltonians for adiabatic quantum computation and its application to finding low energy conformations of lattice protein models

In this report, we explore the use of a quantum optimization algorithm for obtaining low energy conformations of protein models. We discuss mappings between protein models and optimization variables, which are in turn mapped to a system of coupled quantum bits. General strategies are given for constructing Hamiltonians to be used to solve optimization problems of physical/chemical/biological interest via quantum computation by adiabatic evolution. As an example, we implement the Hamiltonian corresponding to the Hydrophobic-Polar (HP) model for protein folding. Furthermore, we present an approach to reduce the resulting Hamiltonian to two-body terms gearing towards an experimental realization.Comment: 35 pages, 8 figure

Introduction to Logic Circuits & Logic Design with Verilog

The overall goal of this book is to fill a void that has appeared in the instruction of digital circuits over the past decade due to the rapid abstraction of system design. Up until the mid-1980s, digital circuits were designed using classical techniques. Classical techniques relied heavily on manual design practices for the synthesis, minimization, and interfacing of digital systems. Corresponding to this design style, academic textbooks were developed that taught classical digital design techniques. Around 1990, large-scale digital systems began being designed using hardware description languages (HDL) and automated synthesis tools. Broad-scale adoption of this modern design approach spread through the industry during this decade. Around 2000, hardware description languages and the modern digital design approach began to be taught in universities, mainly at the senior and graduate level. There were a variety of reasons that the modern digital design approach did not penetrate the lower levels of academia during this time. First, the design and simulation tools were difficult to use and overwhelmed freshman and sophomore students. Second, the ability to implement the designs in a laboratory setting was infeasible. The modern design tools at the time were targeted at custom integrated circuits, which are cost- and time-prohibitive to implement in a university setting. Between 2000 and 2005, rapid advances in programmable logic and design tools allowed the modern digital design approach to be implemented in a university setting, even in lower-level courses. This allowed students to learn the modern design approach based on HDLs and prototype their designs in real hardware, mainly fieldprogrammable gate arrays (FPGAs). This spurred an abundance of textbooks to be authored, teaching hardware description languages and higher levels of design abstraction. This trend has continued until today. While abstraction is a critical tool for engineering design, the rapid movement toward teaching only the modern digital design techniques has left a void for freshman- and sophomore-level courses in digital circuitry. Legacy textbooks that teach the classical design approach are outdated and do not contain sufficient coverage of HDLs to prepare the students for follow-on classes. Newer textbooks that teach the modern digital design approach move immediately into high-level behavioral modeling with minimal or no coverage of the underlying hardware used to implement the systems. As a result, students are not being provided the resources to understand the fundamental hardware theory that lies beneath the modern abstraction such as interfacing, gate-level implementation, and technology optimization. Students moving too rapidly into high levels of abstraction have little understanding of what is going on when they click the “compile and synthesize” button of their design tool. This leads to graduates who can model a breadth of different systems in an HDL but have no depth into how the system is implemented in hardware. This becomes problematic when an issue arises in a real design and there is no foundational knowledge for the students to fall back on in order to debug the problem

Computer Implemented Synthesis of Multiple Level Combinational Networks

The purpose of this investigation has been to implement, in the form of computer programs, two algorithms which are used in the synthesis of multiple level combinational networks. The algorithms implemented were devised by Professor Paul E. Wood, Jr., of M.I.T., and by Professor Eugene L. Lawler, of The University of Michigan. In the course of the investigation a more efficient way of implementing the two algorithms was discovered. The combined version of the algorithms takes advantage of the best features of the original algorithms. In the synthesis of multiple level combinational networks minimal complexity is high desirable. The whole point of minimizing a network is that this leads to lower manufacturing cost, greater ease of construction, and greater reliability for the electronic circuit being designed. The computer programs which were developed to implement the algorithms can minimize Boolean expressions with as many as seven variables. Theoretically, there is no limit to the number of variables per expression that can be minimized by these algorithms. But when an expression has more than seven variables, the processing time increases dramatically, and for this reason this number was set as a limit. The final solutions obtained from the compute programs are minimal two and three level multiple-input single-output Boolean expressions which realize a given set of conditions

Reliability Analysis of a Multi-State Truly-Threshold System Using a Multi-Valued Karnaugh Map

This paper deals with the Boolean-based analysis of a prominent class of non-repairable coherent multistate systems with independent nonidentical multistate components. This class of systems is represented by a multistate coherent truly threshold system of several states, which is not necessarily binary-imaged. The paper represents such a system via Boolean expressions of system success or system failure at each non-zero level, which are in the form of minimal sop formulas, or disjoint sop formulas. These are expressions that are directly convertible to expected values. Several map representations are also offered, including a single multi-value Karnaugh map.Comment: 42 pages, 11 figures, 5 table

Logic Meets Algebra: the Case of Regular Languages

The study of finite automata and regular languages is a privileged meeting point of algebra and logic. Since the work of Buchi, regular languages have been classified according to their descriptive complexity, i.e. the type of logical formalism required to define them. The algebraic point of view on automata is an essential complement of this classification: by providing alternative, algebraic characterizations for the classes, it often yields the only opportunity for the design of algorithms that decide expressibility in some logical fragment. We survey the existing results relating the expressibility of regular languages in logical fragments of MSO[S] with algebraic properties of their minimal automata. In particular, we show that many of the best known results in this area share the same underlying mechanics and rely on a very strong relation between logical substitutions and block-products of pseudovarieties of monoid. We also explain the impact of these connections on circuit complexity theory.Comment: 37 page