High-level synthesis under I/O Timing and Memory constraints

The design of complex Systems-on-Chips implies to take into account communication and memory access constraints for the integration of dedicated hardware accelerator. In this paper, we present a methodology and a tool that allow the High-Level Synthesis of DSP algorithm, under both I/O timing and memory constraints. Based on formal models and a generic architecture, this tool helps the designer to find a reasonable trade-off between both the required I/O timing behavior and the internal memory access parallelism of the circuit. The interest of our approach is demonstrated on the case study of a FFT algorithm

SOMA A Tool for Synthesizing and Optimizing Memory Accesses in ASICs

Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOMA, a synthesis framework for constructing Memory Access Network (MAN) architectures that inherently enforce memory consistency in the presence of dynamic memory access dependencies. A fundamental bottleneck in any such network is arbitrating between concurrent accesses to a shared memory resource. To alleviate this bottleneck, SOMA uses an application-specific concurrency analysis technique to predict the dynamic memory parallelism profile of the application. This is then used to customize the MAN architecture. Depending on the parallelism profile, the MAN may be optimized for latency, throughput or both. The optimized MAN is automatically synthesized into gate-level structural Verilog using a flexible library of network building blocks. SOMA has been successfully integrated into an automated C-to-hardware synthesis flow, which generates standard cell circuits from unrestricted ANSI-C programs. Post-layout experiments demonstrate that application specific MAN construction significantly improves power and performance

Synthèse comportementale sous contraintes de communication et de placement mémoire pour les composants du TDSI

La conception de systèmes complexes en traitement de l'image et du signal implique de réduire les coûts architecturaux et de maximiser les performances temporelles tout en considérant les contraintes de communication et d'accès mémoire durant la conception et l'intégration d'accélérateurs matériels dédiés. Malheureusement, les blocs matériels utilisés dans les flots de conception semi-automatiques traditionnels n'autorisent pas une flexibilité suffisante pour garantir cet objectif. Dans cet article, nous présentons une méthodologie et un outil qui autorisent la synthèse d'applications en traitement du signal et de l'image sous contraintes de communication et de mémorisation. Basé sur un ensemble de modèles formels, notre outil GAUT aide le concepteur à trouver un compromis entre performance et complexité architecturale

Memory Accesses management during High Level Synthesis

ISBN : 1-58113-937-3We introduce a new approach to take into account the memory architecture and the memory mapping in behavioral synthesis. We formalize the memory mapping as a set of constraints for the synthesis, and defined a Memory Constraint Graph and an accessibility criterion to be used in the scheduling step. We present a new strategy for implementing signals (ageing vectors). We formalize the maturing process and explain how it may generate memory conflicts over several iterations of the algorithm. The final Compatibility Graph indicates the set of valid mappings for every signal. Several experiments are performed with our HLS tool GAUT. Our scheduling algorithm exhibits a relatively low complexity that permits to tackle complex designs in a reasonable time