Characterizing and Subsetting Big Data Workloads

Big data benchmark suites must include a diversity of data and workloads to be useful in fairly evaluating big data systems and architectures. However, using truly comprehensive benchmarks poses great challenges for the architecture community. First, we need to thoroughly understand the behaviors of a variety of workloads. Second, our usual simulation-based research methods become prohibitively expensive for big data. As big data is an emerging field, more and more software stacks are being proposed to facilitate the development of big data applications, which aggravates hese challenges. In this paper, we first use Principle Component Analysis (PCA) to identify the most important characteristics from 45 metrics to characterize big data workloads from BigDataBench, a comprehensive big data benchmark suite. Second, we apply a clustering technique to the principle components obtained from the PCA to investigate the similarity among big data workloads, and we verify the importance of including different software stacks for big data benchmarking. Third, we select seven representative big data workloads by removing redundant ones and release the BigDataBench simulation version, which is publicly available from http://prof.ict.ac.cn/BigDataBench/simulatorversion/.Comment: 11 pages, 6 figures, 2014 IEEE International Symposium on Workload Characterizatio

Roadmap to Majorana surface codes

Surface codes offer a very promising avenue towards fault-tolerant quantum computation. We argue that two-dimensional interacting networks of Majorana bound states in topological superconductor/semiconductor heterostructures hold several distinct advantages in that direction, both concerning the hardware realization and the actual operation of the code. We here discuss how topologically protected logical qubits in this Majorana surface code architecture can be defined, initialized, manipulated, and read out. All physical ingredients needed to implement these operations are routinely used in topologically trivial quantum devices. In particular, we show that by means of quantum interference terms in linear conductance measurements, composite single-electron pumping protocols, and gate-tunable tunnel barriers, the full set of quantum gates required for universal quantum computation can be implemented.Comment: 23 pages, 8 figure

Cross-verification of independent quantum devices

Quantum computers are on the brink of surpassing the capabilities of even the most powerful classical computers. This naturally raises the question of how one can trust the results of a quantum computer when they cannot be compared to classical simulation. Here we present a verification technique that exploits the principles of measurement-based quantum computation to link quantum circuits of different input size, depth, and structure. Our approach enables consistency checks of quantum computations within a device, as well as between independent devices. We showcase our protocol by applying it to five state-of-the-art quantum processors, based on four distinct physical architectures: nuclear magnetic resonance, superconducting circuits, trapped ions, and photonics, with up to 6 qubits and 200 distinct circuits

Full-Stack, Real-System Quantum Computer Studies: Architectural Comparisons and Design Insights

In recent years, Quantum Computing (QC) has progressed to the point where small working prototypes are available for use. Termed Noisy Intermediate-Scale Quantum (NISQ) computers, these prototypes are too small for large benchmarks or even for Quantum Error Correction, but they do have sufficient resources to run small benchmarks, particularly if compiled with optimizations to make use of scarce qubits and limited operation counts and coherence times. QC has not yet, however, settled on a particular preferred device implementation technology, and indeed different NISQ prototypes implement qubits with very different physical approaches and therefore widely-varying device and machine characteristics. Our work performs a full-stack, benchmark-driven hardware-software analysis of QC systems. We evaluate QC architectural possibilities, software-visible gates, and software optimizations to tackle fundamental design questions about gate set choices, communication topology, the factors affecting benchmark performance and compiler optimizations. In order to answer key cross-technology and cross-platform design questions, our work has built the first top-to-bottom toolflow to target different qubit device technologies, including superconducting and trapped ion qubits which are the current QC front-runners. We use our toolflow, TriQ, to conduct {\em real-system} measurements on 7 running QC prototypes from 3 different groups, IBM, Rigetti, and University of Maryland. From these real-system experiences at QC's hardware-software interface, we make observations about native and software-visible gates for different QC technologies, communication topologies, and the value of noise-aware compilation even on lower-noise platforms. This is the largest cross-platform real-system QC study performed thus far; its results have the potential to inform both QC device and compiler design going forward.Comment: Preprint of a publication in ISCA 201

Demonstration of Universal Parametric Entangling Gates on a Multi-Qubit Lattice

We show that parametric coupling techniques can be used to generate selective entangling interactions for multi-qubit processors. By inducing coherent population exchange between adjacent qubits under frequency modulation, we implement a universal gateset for a linear array of four superconducting qubits. An average process fidelity of $\mathcal{F}=93\%$ is estimated for three two-qubit gates via quantum process tomography. We establish the suitability of these techniques for computation by preparing a four-qubit maximally entangled state and comparing the estimated state fidelity against the expected performance of the individual entangling gates. In addition, we prepare an eight-qubit register in all possible bitstring permutations and monitor the fidelity of a two-qubit gate across one pair of these qubits. Across all such permutations, an average fidelity of $\mathcal{F}=91.6\pm2.6\%$ is observed. These results thus offer a path to a scalable architecture with high selectivity and low crosstalk