Design of an embedded iris recognition system for use with a multi-factor authentication system.

This paper describes in detail the design, manufacturing and testing of an embedded iris scanner for use with a multifactor authentication system. The design process for this project included hardware design from part selection to board design to populating. Additionally, this process included the entirety of the software development, though the iris recognition process was largely based on other works. The functional requirements for the overall multi-factor authentication system were to have three authentication methods with a thirty second window to complete all three. The system acceptance accuracy was required to be greater than 75%. Those requirements therefore dictate that the iris scanner module must also have an acceptance accuracy higher than 75% and perform iris recognition in a few seconds so that the user can gain admittance in the allotted window of time. While the hardware has been verified and tested, further development and testing is necessary on the software and image processing. This work is funded by the Department of Energy’s Kansas City National Security Campus, operated by Honeywell Federal Manufacturing & Technologies, LLC under contract number DE-NA0002839

Limits on Fundamental Limits to Computation

An indispensable part of our lives, computing has also become essential to industries and governments. Steady improvements in computer hardware have been supported by periodic doubling of transistor densities in integrated circuits over the last fifty years. Such Moore scaling now requires increasingly heroic efforts, stimulating research in alternative hardware and stirring controversy. To help evaluate emerging technologies and enrich our understanding of integrated-circuit scaling, we review fundamental limits to computation: in manufacturing, energy, physical space, design and verification effort, and algorithms. To outline what is achievable in principle and in practice, we recall how some limits were circumvented, compare loose and tight limits. We also point out that engineering difficulties encountered by emerging technologies may indicate yet-unknown limits.Comment: 15 pages, 4 figures, 1 tabl

On-a-chip microdischarge thruster arrays inspired by photonic device technology for plasma television

This study shows that the practical scaling of a hollow cathode thruster device to MEMS level should be possible albeit with significant divergence from traditional design. The main divergence is the need to operate at discharge pressures between 1-3bar to maintain emitter diameter pressure products of similar values to conventional hollow cathode devices. Without operating at these pressures emitter cavity dimensions become prohibitively large for maintenance of the hollow cathode effect and without which discharge voltage would be in the hundreds of volts as with conventional microdischarge devices. In addition this requires sufficiently constrictive orifice diameters in the 10µm – 50µm range for single cathodes or <5µm larger arrays. Operation at this pressure results in very small Debye lengths (4 -5.2pm) and leads to large reductions in effective work function (0.3 – 0.43eV) via the Schottky effect. Consequently, simple work function lowering compounds such as lanthanum hexaboride (LaB6) can be used to reduce operating temperature without the significant manufacturing complexity of producing porous impregnated thermionic emitters as with macro scale hollow cathodes, while still operating <1200°C at the emitter surface. The literature shows that LaB6 can be deposited using a variety of standard microfabrication techniques

Monolithic microwave integrated circuits: Interconnections and packaging considerations

Monolithic microwave integrated circuits (MMIC's) above 18 GHz were developed because of important potential system benefits in cost reliability, reproducibility, and control of circuit parameters. The importance of interconnection and packaging techniques that do not compromise these MMIC virtues is emphasized. Currently available microwave transmission media are evaluated to determine their suitability for MMIC interconnections. An antipodal finline type of microstrip waveguide transition's performance is presented. Packaging requirements for MMIC's are discussed for thermal, mechanical, and electrical parameters for optimum desired performance

E-QED: Electrical Bug Localization During Post-Silicon Validation Enabled by Quick Error Detection and Formal Methods

During post-silicon validation, manufactured integrated circuits are extensively tested in actual system environments to detect design bugs. Bug localization involves identification of a bug trace (a sequence of inputs that activates and detects the bug) and a hardware design block where the bug is located. Existing bug localization practices during post-silicon validation are mostly manual and ad hoc, and, hence, extremely expensive and time consuming. This is particularly true for subtle electrical bugs caused by unexpected interactions between a design and its electrical state. We present E-QED, a new approach that automatically localizes electrical bugs during post-silicon validation. Our results on the OpenSPARC T2, an open-source 500-million-transistor multicore chip design, demonstrate the effectiveness and practicality of E-QED: starting with a failed post-silicon test, in a few hours (9 hours on average) we can automatically narrow the location of the bug to (the fan-in logic cone of) a handful of candidate flip-flops (18 flip-flops on average for a design with ~ 1 Million flip-flops) and also obtain the corresponding bug trace. The area impact of E-QED is ~2.5%. In contrast, deter-mining this same information might take weeks (or even months) of mostly manual work using traditional approaches

A comparison of industrial location behaviour within the US and European Semicondictor Industries

Our paper analyses micro-level data from the US and European semiconductor manufacturers. In particular, we will focus on the plants undertaking the wafer manufacturing processes. We integrate a range of production technological indices with spatial data and regional economic variables in order to understand the issues determining the location behavior of the industry. Our results indicate that the locational behaviors of the US and European wafer plants do not correspond to an orthodox product-life-cycle model.