210,123 research outputs found
A Logic Simplification Approach for Very Large Scale Crosstalk Circuit Designs
Crosstalk computing, involving engineered interference between nanoscale
metal lines, offers a fresh perspective to scaling through co-existence with
CMOS. Through capacitive manipulations and innovative circuit style, not only
primitive gates can be implemented, but custom logic cells such as an Adder,
Subtractor can be implemented with huge gains. Our simulations show over 5x
density and 2x power benefits over CMOS custom designs at 16nm [1]. This paper
introduces the Crosstalk circuit style and a key method for large-scale circuit
synthesis utilizing existing EDA tool flow. We propose to manipulate the CMOS
synthesis flow by adding two extra steps: conversion of the gate-level netlist
to Crosstalk implementation friendly netlist through logic simplification and
Crosstalk gate mapping, and the inclusion of custom cell libraries for
automated placement and layout. Our logic simplification approach first
converts Cadence generated structured netlist to Boolean expressions and then
uses the majority synthesis tool to obtain majority functions, which is further
used to simplify functions for Crosstalk friendly implementations. We compare
our approach of logic simplification to that of CMOS and majority logic-based
approaches. Crosstalk circuits share some similarities to majority synthesis
that are typically applied to Quantum Cellular Automata technology. However,
our investigation shows that by closely following Crosstalk's core circuit
styles, most benefits can be achieved. In the best case, our approach shows 36%
density improvements over majority synthesis for MCNC benchmark
Majority logic synthesis
International audienceThe majority function ⟨xyz⟩ evaluates to true, if at least two of its Boolean inputs evaluate to true. The majority function has frequently been studied as a central primitive in logic synthesis applications for many decades. Knuth refers to the majority function in the last volume of his seminal The Art of Computer Programming as "probably the most important ternary operation in the entire universe. " Majority logic sythesis has recently regained signficant interest in the design automation community due to nanoemerging technologies which operate based on the majority function. In addition , majority logic synthesis has successfully been employed in CMOS-based applications such as standard cell or FPGA mapping. This tutorial gives a broad introduction into the field of majority logic synthesis. It will review fundamental results and describe recent contributions from theory, practice, and applications
Integrating nano-logic into an undergraduate logic design course
The goal of this work is to motivate our students and enhance their ability to address newer logic blocks namely majority gates in the existing framework. We use a K-map based methodology to introduce a few novel nano-logic design concepts for the undergraduate logic design class. We want them to possess knowledge about a few fundamental abstracted logical behaviors of future nano-devices and their functionality which in turn would motivate them to further investigate these non-CMOS emerging devices, logics and architectures. This would augment critical thinking of the students where they apply the learnt knowledge to a novel/unfamiliar situation. We intend to augment the existing standard EE and CS courses by inserting K-map based knowledge modules on nano-logic structure for stimulating their interest without significant diversion from the course framework. Experiments with our students show that all the students were able to grasp the basic concept of majority logic synthesis and almost 63 of them had a deeper understanding of the synthesis algorithm demonstrated to them
Mathematical Estimation of Logical Masking Capability of Majority/Minority Gates Used in Nanoelectronic Circuits
In nanoelectronic circuit synthesis, the majority gate and the inverter form
the basic combinational logic primitives. This paper deduces the mathematical
formulae to estimate the logical masking capability of majority gates, which
are used extensively in nanoelectronic digital circuit synthesis. The
mathematical formulae derived to evaluate the logical masking capability of
majority gates holds well for minority gates, and a comparison with the logical
masking capability of conventional gates such as NOT, AND/NAND, OR/NOR, and
XOR/XNOR is provided. It is inferred from this research work that the logical
masking capability of majority/minority gates is similar to that of XOR/XNOR
gates, and with an increase of fan-in the logical masking capability of
majority/minority gates also increases
Work in progress: introduction of K-map based nano-logic synthesis as knowledge module in logic design course
This work in progress reports an effort of introducing knowledge module regarding novel nano-devices and novel logic primitives in undergraduate logic design class. Our motivation is to make our students aware of fundamental abstracted logical behaviors of future nano-devices, their functionality. This effort would also help the students use their existing knowledge of K-map based logical synthesis into constructing logic blocks for novel devices that uses majority logic as basic construct. Moreover, additional to stimulating our students' interests, we are also augmenting their learning by challenging them to use their existing knowledge to analyze, synthesize and comprehend novel nano-logic issues through the worksheets and lecture modules. Whereas many efforts are focusing on developing new courses on nanofabrication and even nano-computing, we intend to augment the existing standard EE and CS courses by inserting knowledge modules on nano-logic structure for stimulating their interest without significant diversion from the course framework
Majority-based Synthesis for Nanotechnologies
We study the logic synthesis of emerging nanotechnologies whose elementary devices abstraction is a majority voter. We argue that synthesis tools, natively supporting the majority logic abstraction, are the technology enablers. This is because they allow designers to validate majority-based nanotechnologies on large-scale benchmarks. We describe models and data-structures for logic design with majority-based nanotechnologies and we show results of applying new synthesis algorithms and tools. We conclude that new logic synthesis methods are required to achieve a fair assessment on emerging nanotechnologies
Majority Logic Synthesis for Spin Wave Technology
Spin Wave Devices (SWDs) are promising beyond-CMOS candidates. Unlike traditional charge-based technologies, SWDs use spin as information carrier that propagates in waves. In this scenario, the logic primitive for computation is the majority gate. The majority gate has a greater expressive power than standard NAND/NOR gates, allowing SWD circuits to be more compact than CMOS, already at the logic level. Also, because there is not charge carrier transport, SWDs are estimated to have ultra-low power consumption. However, in order to exploit this opportunity, a native majority synthesis methodology is needed to fit the SWD technology needs. In this paper, we employ Majority-Inverter Graphs (MIGs) to naturally represent and synthesize SWD circuits. Thanks to the correspondence between the functionality of SWD primitive gates and MIG elements, MIG optimization intrinsically aims at minimum cost SWD implementations. Experimental results over MCNC benchmarks validate the efficiency of MIGs in SWD synthesis. As compared to traditional AND-Inverter Graph (AIG) synthesis, MIGs generate, on average, SWD circuits with 1.30Ă— smaller area-delay-power product (ADP), improving their delay performance by 18%
- …