Design of a SRAM memory controller and interface for in-memory computing applications

Recently, neural networks have gained much attention, due to their high effectiveness. Their operation principle is based on massively parallel calculations, which possess a challenge for classical computing architectures, based on the Von Neumann principle, which uses separate memory and computing units. Due to low throughput of interconnections between these two systems (the so called Von-Neumann bottleneck) neural net-works cannot be effectively computed by these classical architectures. Therefore, many in-memory-computing architectures, where many computations are performed inside memory, have been recently proposed to solve this issue. In-memory-computing system provides efficient implementation of massively parallel computation. However, providing necessary weights of neural networks into the computing units poses challenges, as memory is typically too small to fit all weights and perform all computations at once. Yet, finding efficient ways of loading weights into this memory has not been extensively researched. For that reason, this thesis focuses on design of memory controller, that is used in in-memory-computing architecture for transferring weights into the under-lying memory. Specifically, several controller topologies are compared, and one selected design is simulated in the context of an in-memory computing matrix. In addition, this thesis provides an extensive theory background of IMC system, namely its variations, basic building blocks, advantages and disadvantages