16 research outputs found
Integer Linear Programming Modeling of Addition Sequences With Additional Constraints for Evaluation of Power Terms
In this work, an integer linear programming (ILP) based model is proposed for
the computation of a minimal cost addition sequence for a given set of
integers. Since exponents are additive under multiplication, the minimal length
addition sequence will provide an economical solution for the evaluation of a
requested set of power terms. This is turn, finds application in, e.g.,
window-based exponentiation for cryptography and polynomial evaluation. Not
only is an optimal model proposed, the model is extended to consider different
costs for multipliers and squarers as well as controlling the depth of the
resulting addition sequence.Comment: This manuscript was written in 2012, and, hence, lacks more recent
reference
A new Low-Power recoding algorithm for multiplierless single/multiple constant multiplication.
International audienceOptimizing the number of additions in constant coefficient multiplication is conjectured to be a NP-hard problem. In this paper, we report a new heuristic requiring an average of 29.10 % and 10.61 % less additions than the standard canonical signed digit representation (CSD) and the double base number system (DBNS), respectively, for 64-bit coefficients. The maximum number of additions per coefficient is bounded by (N/4)+2, and the time-complexity of the recoding is linearly proportional to N, where N is the bit-size of the constant. These performances are achieved using a new redundant version of radix-28 recoding
Multiplication by rational constants: LIP research report 2011-3
International audienceMultiplications by simple rational constants often appear in fixed-point or floating-point application code, for instance in the form of division by an integer constant. The hardware implementation of such operations is of practical interest to FPGA-accelerated computing. It is well known that the binary representation of rational constants is eventually periodic. This article shows how this feature can be exploited to implement multiplication by a rational constant in a number of additions that is logarithmic in the precision. An open-source implementation of these techniques is provided, and is shown to be practically relevant for constants with small numerators and denominators, where it provides improvements of 20 to 40\% in area with respect to the state of the art. It is also shown that for such constants, the additional cost for a correctly rounded result is very small, and that correct rounding very often comes for free in practice
Radix-2r Arithmetic for Multiplication by a Constant.
International audienceIn this paper, radix-2r arithmetic is explored to minimize the number of additions in the multiplication by a constant. We provide the formal proof that for an N-bit constant, the maximum number of additions using radix-2r is lower than Dimitrov's estimated upper-bound (2.N/log(N)) using double base number system (DBNS). In comparison to canonical signed digit (CSD) and DBNS, the new radix-2r recoding requires an average of 23.12% and 3.07% less additions for 64-bit constant, respectively
IMPLEMENTATION OF HIGH-SPEED MULTIPLIER FILTERS USING A MODIFIED NON RECURSIVE COMMON DADA MULTIPLIER
A multiplier is one of the key hardware blocks in most digital signal processing (DSP) systems. Typical DSP applications where a multiplier plays an important role include digital filtering, digital communications and spectral analysis (Ayman.A et al (2001)). Many current DSP applications are targeted at portable, battery-operated systems, so that power dissipation becomes one of the primary design constraints. Since multipliers are rather complex circuits and must typically operate at a high system clock rate, reducing the delay of a multiplier is an essential part of satisfying the overall design. In this project two different multipliers are designed which are array multiplier and modified dada multiplier along with the combination of truncated multiplier. The comparison is carried out using the EDA tool XILINX ISE 12.3i by developing the RTL (Register Transfer Level) using the VERILOG HDL
Towards the Multiple Constant Multiplication at Minimal Hardware Cost
Multiple Constant Multiplication (MCM) over integers is a frequent operation
arising in embedded systems that require highly optimized hardware. An
efficient way is to replace costly generic multiplication by bit-shifts and
additions, i.e. a multiplierless circuit. In this work, we improve the
state-of-the-art optimal approach for MCM, based on Integer Linear Programming
(ILP). We introduce a new lower-level hardware cost, based on counting the
number of one-bit adders and demonstrate that it is strongly correlated with
the LUT count. This new model for the multiplierless MCM circuits permitted us
to consider intermediate truncations that permit to significantly save
resources when a full output precision is not required. We incorporate the
error propagation rules into our ILP model to guarantee a user-given error
bound on the MCM results. The proposed ILP models for multiple flavors of MCM
are implemented as an open-source tool and, combined with the FloPoCo code
generator, provide a complete coefficient-to-VHDL flow. We evaluate our models
in extensive experiments, and propose an in-depth analysis of the impact that
design metrics have on actually synthesized hardware.Comment: 10 pages, 3 tables, 6 figures, journal submissio
LOW POWER MULTIPLIER USING ALGORITHMIC NOISE TOLERANT ARCHITECTURE
: A multiplier is one of the key hardware blocks in most digital signal processing (DSP) systems. Typical DSP applications where a multiplier plays an important role include digital filtering, digital communications and spectral analysis (Ayman.A et al (2001)). Many current DSP applications are targeted at portable, battery-operated systems, so that power dissipation becomes one of the primary design constraints. Since multipliers are rather complex circuits and must typically operate at a high system clock rate, reducing the delay of a multiplier is an essential part of satisfying the overall design. In this project a multiplier block has been designed through the algorithmic noise tolerance architectures (ANT) by using Wallace multiplier. A reliable low power multiplier design with the fixed width multiplier block through the reduced precision replica redundancy (RPR) and main block design with Wallace multiplier . The new architecture can meet the high accuracy, low power consumption and area efficiency when compared with previous multiplier circuit