Accurate Settling-Time Modeling and Design Procedures for Two-Stage Miller-Compensated Amplifiers for Switched-Capacitor Circuits

We present modeling techniques for accurate estimation of settling errors in switched-capacitor (SC) circuits built with Miller-compensated operational transconductance amplifiers (OTAs). One distinctive feature of the proposal is the computation of the impact of signal levels (on both the model parameters and the model structure) as they change during transient evolution. This is achieved by using an event-driven behavioral approach that combines small- and large-signal behavioral descriptions and keeps track of the amplifier state after each clock phase. Also, SC circuits are modeled under closed-loop conditions to guarantee that the results remain close to those obtained by electrical simulation of the actual circuits. Based on these models, which can be regarded as intermediate between the more established small-signal approach and full-fledged simulations, design procedures for dimensioning SC building blocks are presented whose targets are system-level specifications (such as ENOB and SNDR) instead of OTA specifications. The proposed techniques allow to complete top-down model-based designs with 0.3-b accuracy.Ministerio de Educación y Ciencia TEC2006-03022Junta de Andalucía TIC-0281

Amplifier performance enhancement methods using positive feedback techniques

The dramatic growth in the hi-tech sector of consumer market has created many unprecedented challenges in the area of integrated circuits. The present and future communication and entertainment systems including high speed cable and DSL modems, broadband wired and wireless systems, and high definition visual products require very fast and high accuracy amplifiers, data converters and filters. Analog design in the new digital CMOS submicron processes is becoming an economical necessity in the industry. The task of building fast Op-Amp with very high DC-gain is already a very difficult problem, and this task has become more difficult using these new submicron digital processes, where traditional gain enhancement techniques are loosing their ability to deliver amplifiers with sufficient gain. In this work three new methods of implementing the internal positive-feedback to build very high DC-gain amplifiers with very low gain sensitivity to signal swings are presented. Amplifiers proposed in the first method have very high current-controlled gain. A DC gain larger than 100dB is possible without limiting the speed of the amplifier. Amplifiers proposed in the second method exhibit both enhanced speed, i.e., unity gain frequency, and enhanced gain. Amplifiers proposed in the third method have self-adjusting gain without extra control block. An implementation of a 3 bit multiplying DAC in a 9-bit 165MS/s pipeline ADC built in a 1.8V, 0.21mu digital CMOS process using one of the proposed amplifiers is described. Test results show high gain with very fast settling

Switched-compensation technique in switched-capacitor circuits for achieving fast settling performance

Resolving stability issue is one of the major challenges in designing a perfect op-amp, the most widely used analog circuit block. Many compensation techniques have been proposed to improve the stability performance of op amps, but virtually all these techniques were developed for continuous-time applications and subsequently applied to discrete-time applications (e.g., switched-capacitor circuits). Since the early 1980s, an increasing number of op-amps have been used in switched-capacitor circuits with no special compensation method applied. Consequently, there remains a need to explore the possibility of designing a unique compensation method specifically for switched-capacitor use. A new switched-compensation technique (SCT) is proposed for switched-capacitor circuit applications in which high speed is a critical index of performance. In general, designers must deal with trade-offs among accuracy, speed, and power dissipation. SCT avoids traditional approaches of designing high-speed, high-gain operational amplifiers that are in many cases technology-limited. Instead, it modifies the switched-capacitor circuit structure to use the under-damped response of the system, usually regarded as a drawback. SCT is introduced as a novel solution for achieving fast settling performance and lower quiescent power dissipation while guaranteeing almost equivalent accuracy. SCT can be easily implemented in flip-around switched-capacitor amplifier circuits. This paper explains SCT principle and implementation applied to multiplying-digital-to-analog converters (MDACs) as a proof of concept. Simulation results based on an IBM 0.13um CMOS process are presented. Compared with a conventional switched-capacitor amplifier, a SCT-based implementation reduces the quiescent power consumption by half and settling time within 1% error by 60%

Low-Power Slew-Rate Boosting Based 12-Bit Pipeline ADC Utilizing Forecasting Technique in the Sub-ADCS

The dissertation presents architecture and circuit solutions to improve the power efficiency of high-speed 12-bit pipelined ADCs in advanced CMOS technologies. First, the 4.5bit algorithmic pipelined front-end stage is proposed. It is shown that the algorithmic pipelined ADC requires a simpler sub-ADC and shows lower sensitivity to the Multiplying DAC (MDAC) errors and smaller area and power dissipation in comparison to the conventional multi-bit per stage pipelined ADC. Also, it is shown that the algorithmic pipelined architecture is more tolerant to capacitive mismatch for the same input-referred thermal noise than the conventional multi-bit per stage architecture. To take full advantage of these properties, a modified residue curve for the pipelined ADC is proposed. This concept introduces better linearity compared with the conventional residue curve of the pipelined ADC; this approach is particularly attractive for the digitization of signals with large peak to average ratio such as OFDM coded signals. Moreover, the minimum total required transconductance for the different architectures of the 12-bit pipelined ADC are computed. This helps the pipelined ADC designers to find the most power-efficient architecture between different topologies based on the same input-referred thermal noise. By employing this calculation, the most power efficient architecture for realizing the 12-bit pipelined ADC is selected. Then, a technique for slew-rate (SR) boosting in switched-capacitor circuits is proposed in the order to be utilized in the proposed 12-bit pipelined ADC. This technique makes use of a class-B auxiliary amplifier that generates a compensating current only when high slew-rate is demanded by large input signal. The proposed architecture employs simple circuitry to detect the need of injecting current at the output load by implementing a Pre-Amp followed by a class-B amplifier, embedded with a pre-defined hysteresis, in parallel with the main amplifier to boost its slew phase. The proposed solution requires small static power since it does not need high dc-current at the output stage of the main amplifier. The proposed technique is suitable for high-speed low-power multi-bit/stage pipelined ADC applications. Both transistor-level simulations and experimental results in TSMC 40nm technology reduces the slew-time for more than 45% and shorts the 1% settling time by 28% when used in a 4.5bit/stage pipelined ADC; power consumption increases by 20%. In addition, the technique of inactivating and disconnecting of the sub-ADC’s comparators by forecasting the sign of the sampled input voltage is proposed in the order to reduce the dynamic power consumption of the sub-ADCs in the proposed 12-bit pipelined ADC. This technique reduces the total dynamic power consumption more than 46%. The implemented 12-bit pipelined ADC achieves an SNDR/SFDR of 65.9/82.3 dB at low input frequencies and a 64.1/75.5 dB near Nyquist frequency while running at 500 MS/s. The pipelined ADC prototype occupies an active area of 0.9 mm^2 and consumes 18.16 mW from a 1.1 V supply, resulting in a figure of merit (FOM) of 22.4 and a 27.7 fJ/conversion-step at low-frequency and Nyquist frequency, respectively

Low-Power Slew-Rate Boosting Based 12-Bit Pipeline ADC Utilizing Forecasting Technique in the Sub-ADCS

The dissertation presents architecture and circuit solutions to improve the power efficiency of high-speed 12-bit pipelined ADCs in advanced CMOS technologies. First, the 4.5bit algorithmic pipelined front-end stage is proposed. It is shown that the algorithmic pipelined ADC requires a simpler sub-ADC and shows lower sensitivity to the Multiplying DAC (MDAC) errors and smaller area and power dissipation in comparison to the conventional multi-bit per stage pipelined ADC. Also, it is shown that the algorithmic pipelined architecture is more tolerant to capacitive mismatch for the same input-referred thermal noise than the conventional multi-bit per stage architecture. To take full advantage of these properties, a modified residue curve for the pipelined ADC is proposed. This concept introduces better linearity compared with the conventional residue curve of the pipelined ADC; this approach is particularly attractive for the digitization of signals with large peak to average ratio such as OFDM coded signals. Moreover, the minimum total required transconductance for the different architectures of the 12-bit pipelined ADC are computed. This helps the pipelined ADC designers to find the most power-efficient architecture between different topologies based on the same input-referred thermal noise. By employing this calculation, the most power efficient architecture for realizing the 12-bit pipelined ADC is selected. Then, a technique for slew-rate (SR) boosting in switched-capacitor circuits is proposed in the order to be utilized in the proposed 12-bit pipelined ADC. This technique makes use of a class-B auxiliary amplifier that generates a compensating current only when high slew-rate is demanded by large input signal. The proposed architecture employs simple circuitry to detect the need of injecting current at the output load by implementing a Pre-Amp followed by a class-B amplifier, embedded with a pre-defined hysteresis, in parallel with the main amplifier to boost its slew phase. The proposed solution requires small static power since it does not need high dc-current at the output stage of the main amplifier. The proposed technique is suitable for high-speed low-power multi-bit/stage pipelined ADC applications. Both transistor-level simulations and experimental results in TSMC 40nm technology reduces the slew-time for more than 45% and shorts the 1% settling time by 28% when used in a 4.5bit/stage pipelined ADC; power consumption increases by 20%. In addition, the technique of inactivating and disconnecting of the sub-ADC’s comparators by forecasting the sign of the sampled input voltage is proposed in the order to reduce the dynamic power consumption of the sub-ADCs in the proposed 12-bit pipelined ADC. This technique reduces the total dynamic power consumption more than 46%. The implemented 12-bit pipelined ADC achieves an SNDR/SFDR of 65.9/82.3 dB at low input frequencies and a 64.1/75.5 dB near Nyquist frequency while running at 500 MS/s. The pipelined ADC prototype occupies an active area of 0.9 mm^2 and consumes 18.16 mW from a 1.1 V supply, resulting in a figure of merit (FOM) of 22.4 and a 27.7 fJ/conversion-step at low-frequency and Nyquist frequency, respectively

Strategies for enhancing DC gain and settling performance of amplifiers

The operational amplifier (op amp) is one of the most widely used and important building blocks in analog circuit design. High gain and high speed are two important properties of op amps because they determine the settling behavior of the op amps. As supply voltages decrease, the realization of high gain amplifiers with large Gain-Bandwidth-Products (GBW) has become challenging. The major focus in this dissertation is on the negative output impedance gain enhancement technique. The negative impedance gain enhancement technique offers potential for achieving very high gain and energy-efficient fast settling and is low-voltage compatible. Misconceptions that have limited the practical adoption of this gain enhancement technique are discussed. A new negative conductance gain enhancement technique was proposed. The proposed circuit generates a negative conductance with matching requirements for achieving very high DC gain that are less stringent than those for existing -g m gain enhancement schemes. The proposed circuit has potential for precise digital control of a very large DC gain. A prototype fully differential CMOS operational amplifier was designed and fabricated based on the proposed gain enhancement technique. Experimental results which showed a DC gain of 85dB and an output swing of 876mVp-p validated the fundamental performance characteristics of this technique. In a separate section, a new amplifier architecture with bandpass feedforward compensation is presented. It is shown that a bandpass feedforward path can be used to substantially extend the unity-gain-frequency of an operational amplifier. Simulation results predict significant improvements in rise time and settling performance and show that the bandpass compensation scheme is reasonably robust. In the final section, a new technique for asynchronous data recovery based upon using a delay line in the incoming data path is introduced. The proposed data recovery system is well suited for tight tolerance channels and coding systems supporting standards that limit the maximum number of consecutive 0\u27s and 1\u27s in a data stream. This system does not require clock recovery, suffers no loss of data during acquisition, has a reduced sensitivity to jitter in the incoming data and does not exhibit jitter enhancement associated with VCO tracking in a PLL

A 90 dB, 85 MHz operational transconductance amplifier (OTA) using gain boosting technique

Gain and speed are the two most important parameters of an amplifier. Optimizing an amplifier for both of these parameters leads to contradicting demands. Various architectures have been reported to obtain high gain from the circuits. Cascode circuits are widely used in circuit design at places where high gain and high output impedances are required. Different architectures like triple cascode topology, dynamic biasing and a positive feedback amplifier have been used to obtain high gains. These architectures have been compared in this thesis along with drawbacks and advantages of each

Performance analysis and design optimization of parallel-type slew-rate enhancers for switched-capacitor applications

The design of single-stage OTAs for accurate switched-capacitor circuits involves challenging trade-offs between speed and power consumption. The addition of a Slew-Rate Enhancer (SRE) circuit placed in parallel to the main OTA (parallel-type SRE) constitutes a viable solution to reduce the settling time, at the cost of low-power overhead and no modifications of the main OTA. In this work, a practical analytical model has been developed to predict the settling time reduction achievable with OTA/SRE systems and to show the effect of the various design parameters. The model has been applied to a real case, consisting of the combination of a standard folded-cascode OTA with an existing parallel-type SRE solution. Simulations performed on a circuit designed with a commercial 180-nm CMOS technology revealed that the actual settling-time reduction was significantly smaller than predicted by the model. This discrepancy was explained by taking into account the internal delays of the SRE, which is exacerbated when a high output current gain is combined with high power efficiency. To overcome this problem, we propose a simple modification of the original SRE circuit, consisting in the addition of a single capacitor which temporarily boosts the OTA/SRE currents reducing the internal turn-on delay. With the proposed approach a settling-time reduction of 57% has been demonstrated with an SRE that introduces only a 10% power-overhead with respect of the single OTA solution. The robustness of the results have been validated by means of Monte-Carlo simulations